ddr2_sdram_cont/dcm_module.v

ソースコードを見る。

関数
default_nettype none timescale KEEP_HIERARCHY module	dcm_module (sysclk, reset, ddr2_clk, ddr2_clkb, clk, clk90, clk1_16, dcm_locked_in, dcm_locked_out)
DCM	DCM_INST1 (.CLKIN(sysclk),.CLKFB(clk_bufg),.DSSEN(1'b0),.PSINCDEC(1'b0),.PSEN(1'b0),.PSCLK(1'b0),.RST(1'b0),.CLK0(clk_node),.CLK90(clk90_node),.CLK180(),.CLK270(),.CLK2X(),.CLK2X180(),.CLKDV(clk1_16_node),.CLKFX(),.CLKFX180(),.LOCKED(dcm1_locked),.PSDONE(),.STATUS())
BUFG	CLK_BUFG_INST (.I(clk_node),.O(clk_bufg))
BUFG	CLK90_BUFG_INST (.I(clk90_node),.O(clk90_bufg))
BUFG	CLK1_16_BUFG_INST (.I(clk1_16_node),.O(clk1_16_bufg))
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	DDR_ALIGNMENT ("NONE")
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	SRTYPE ("SYNC")) ODDR2_CLKB(.Q(ddr2_clkb[i])
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	C0 (clk_bufg)
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	C1 (~clk_bufg)
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	CE (1'b1)
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	D0 (1'b0)
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	D1 (1'b1)
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	R (reset)
for(i=0;i <=QUANTITY_OF_CLK_OUTPUT-1;i=i+1) begin ODDR2	S (1'b0))
変数
include ddr2_cont_parameters vh input wire	sysclk
input wire	reset
output wire[QUANTITY_OF_CLK_OUTPUT-1:0]	ddr2_clk
output wire[QUANTITY_OF_CLK_OUTPUT-1:0]	ddr2_clkb
output wire	clk = clk_bufg
output wire	clk90 = clk90_bufg
output wire	clk1_16 = clk1_16_bufg
input wire	dcm_locked_in
output wire	dcm_locked_out = dcm1_locked
wire	clk_bufg
wire	clk_node
wire	clk90_node
wire	clk1_16_node
wire	dcm1_locked
wire	clk90_bufg
wire	clk1_16_bufg
defparam DCM_INST1	CLKIN_PERIOD = 6.7
defparam DCM_INST1	DLL_FREQUENCY_MODE = "LOW"
defparam DCM_INST1	DUTY_CYCLE_CORRECTION = "TRUE"
defparam DCM_INST1	CLKDV_DIVIDE = 16.0
defparam DCM_INST1	PHASE_SHIFT = 0
defparam DCM_INST1	CLKOUT_PHASE_SHIFT = "NONE"
defparam DCM_INST1	STARTUP_WAIT = "FALSE"
generate genvar	i

関数

for (i=0; i<=QUANTITY_OF_CLK_OUTPUT-1; i=i+1) begin ODDR2 C0 ( clk_bufg )

for (i=0; i<=QUANTITY_OF_CLK_OUTPUT-1; i=i+1) begin ODDR2 C1 ( ~ clk_bufg )

for (i=0; i<=QUANTITY_OF_CLK_OUTPUT-1; i=i+1) begin ODDR2 CE ( 1' b1 )

BUFG CLK1_16_BUFG_INST	(	.	Iclk1_16_node,
		.	Oclk1_16_bufg
	)

BUFG CLK90_BUFG_INST	(	.	Iclk90_node,
		.	Oclk90_bufg
	)

BUFG CLK_BUFG_INST	(	.	Iclk_node,
		.	Oclk_bufg
	)

for (i=0; i<=QUANTITY_OF_CLK_OUTPUT-1; i=i+1) begin ODDR2 D0 ( 1' b0 )

for (i=0; i<=QUANTITY_OF_CLK_OUTPUT-1; i=i+1) begin ODDR2 D1 ( 1' b1 )

DCM DCM_INST1	(	.	CLKINsysclk,
		.	CLKFBclk_bufg,
		.	DSSEN1'b0,
		.	PSINCDEC1'b0,
		.	PSEN1'b0,
		.	PSCLK1'b0,
		.	RST1'b0,
		.	CLK0clk_node,
		.	CLK90clk90_node,
		.	CLK180(),
		.	CLK270(),
		.	CLK2X(),
		.	CLK2X180(),
		.	CLKDVclk1_16_node,
		.	CLKFX(),
		.	CLKFX180(),
		.	LOCKEDdcm1_locked,
		.	PSDONE(),
		.	STATUS()
	)