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00006 `default_nettype none
00007 `timescale 1ns / 1ps
00008
00009 module read_write_io (reset, clk, clk90, read_timing, read_timing_1b, read_timing_2b, burst_read, output_data, rddata_valid, wrdata_fifo_data, wrdata_fifo_mask, dqs_enable, dqs_reset, ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_dm, sd_loop_in, sd_loop_out);
00010 `include "./ddr2_cont_parameters.vh"
00011 input wire reset;
00012 input wire clk;
00013 input wire clk90;
00014 input wire read_timing;
00015 input wire read_timing_1b;
00016 input wire read_timing_2b;
00017 input wire burst_read;
00018 output wire [INTERFACE_DATA_WIDTH-1 : 0] output_data;
00019 output wire rddata_valid;
00020
00021 input wire [INTERFACE_DATA_WIDTH-1 : 0] wrdata_fifo_data;
00022 input wire [INTERFACE_MASK_WIDTH-1 : 0] wrdata_fifo_mask;
00023 input wire dqs_enable;
00024 input wire dqs_reset;
00025
00026 inout wire [DDR2_DATA_WIDTH-1: 0] ddr2_dq;
00027 inout wire [DDR2_DQS_DM_WIDTH-1: 0] ddr2_dqs;
00028 inout wire [DDR2_DQS_DM_WIDTH-1: 0] ddr2_dqs_n;
00029 output wire [DDR2_DQS_DM_WIDTH-1: 0] ddr2_dm;
00030 input wire sd_loop_in;
00031 output wire sd_loop_out;
00032
00033 wire clkx, clk270;
00034 wire [DDR2_DATA_WIDTH-1: 0] dq_tri_d0;
00035 wire [DDR2_DATA_WIDTH-1: 0] dq_tri_d1;
00036 wire [DDR2_DATA_WIDTH-1: 0] dq_tri_ce;
00037 wire [DDR2_DATA_WIDTH-1: 0] dq_data_d0;
00038 wire [DDR2_DATA_WIDTH-1: 0] dq_data_d1;
00039 wire [DDR2_DATA_WIDTH-1: 0] dq_data_ce;
00040 wire [DDR2_DQS_DM_WIDTH-1: 0] dqs_reset_io;
00041 wire [DDR2_DQS_DM_WIDTH-1: 0] dqs_enable_io;
00042 wire [DDR2_DQS_DM_WIDTH-1: 0] dm_data_d0;
00043 wire [DDR2_DQS_DM_WIDTH-1: 0] dm_data_d1;
00044 wire [DDR2_DQS_DM_WIDTH-1: 0] dm_data_ce;
00045 wire fb_read_timing;
00046 reg rdd_afifo_rd_en;
00047 wire rdd_afifo_empty;
00048 wire rdd_afifo_almost_empty;
00049 wire rdd_afifo_full;
00050 wire rdd_afifo_almost_full;
00051 reg [INTERFACE_DATA_WIDTH-1 : 0] wrdata_1d;
00052 reg [INTERFACE_DATA_WIDTH-1 : 0] wrdata_2d;
00053 reg [INTERFACE_DATA_WIDTH-1 : 0] wrdata_3d;
00054 reg [INTERFACE_DATA_WIDTH-1 : 0] wrdata_4d;
00055 reg [INTERFACE_DATA_WIDTH/2-1 : 0] wrdata_3d_half;
00056 reg [INTERFACE_DATA_WIDTH/2-1 : 0] wrdata_4d_half;
00057 reg [INTERFACE_DATA_WIDTH/2-1 : 0] wrdata_5d_half;
00058 reg [INTERFACE_MASK_WIDTH-1 : 0] wrmask_1d;
00059 reg [INTERFACE_MASK_WIDTH-1 : 0] wrmask_2d;
00060 reg [INTERFACE_MASK_WIDTH-1 : 0] wrmask_3d;
00061 reg [INTERFACE_MASK_WIDTH-1 : 0] wrmask_4d;
00062 reg [INTERFACE_MASK_WIDTH/2-1 : 0] wrmask_3d_half;
00063 reg [INTERFACE_MASK_WIDTH/2-1 : 0] wrmask_4d_half;
00064 reg [INTERFACE_MASK_WIDTH/2-1 : 0] wrmask_5d_half;
00065 wire [DDR2_DQS_DM_WIDTH-1 : 0] dqs_out;
00066 wire gnd, vcc;
00067 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_1d;
00068 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_2d;
00069 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_3d;
00070 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_1d_dq;
00071 reg [DDR2_DATA_WIDTH-1 : 0] dqs_enable_2d_dq;
00072 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_2d_mask;
00073 reg [DDR2_DATA_WIDTH-1 : 0] dqs_enable_3d_dq;
00074 reg [DDR2_DATA_WIDTH-1 : 0] dqs_enable_4d_dq;
00075 reg [DDR2_DATA_WIDTH-1 : 0] dqs_enable_4d_dq_clk90;
00076 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_3d_mask;
00077 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_4d_mask_clk90;
00078 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_reset_1d;
00079 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_reset_2d;
00080 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_reset_3d;
00081 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_reset_1d_dq;
00082 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_reset_2d_dq;
00083 reg [DDR2_DATA_WIDTH-1 : 0] dqs_reset_2d_dqtri;
00084 reg [DDR2_DQS_DM_WIDTH-1 : 0] dqs_reset_3d_dq;
00085 reg [DDR2_DATA_WIDTH-1 : 0] dqs_reset_3d_dqtri;
00086 wire [INTERFACE_DATA_WIDTH-1 : 0] dout;
00087 reg [INTERFACE_DATA_WIDTH-1 : 0] dout_node;
00088 reg valid_node;
00089 wire [DDR2_DATA_WIDTH-1: 0] dq_data;
00090 wire dqs_clk;
00091 wire [DDR2_DQS_DM_WIDTH-1 : 0] dqs_enable_node;
00092
00093 assign clkx = ~clk;
00094 assign clk270 = ~clk90;
00095
00096
00097 always @ (posedge clk) begin
00098 if (reset) begin
00099 wrdata_1d <= 0;
00100 wrmask_1d <= 0;
00101 end else begin
00102 wrdata_1d <= wrdata_fifo_data;
00103 wrmask_1d <= wrdata_fifo_mask;
00104 end
00105 end
00106
00107
00108 always @ (posedge clk270) begin
00109 if (reset==1'b1) begin
00110 wrdata_2d <= 0;
00111 wrmask_2d <= 0;
00112 wrdata_3d_half <= 0;
00113 wrmask_3d_half <= 0;
00114 wrdata_3d <= 0;
00115 wrdata_4d_half <= 0;
00116 wrmask_3d <= 0;
00117 wrmask_4d_half <= 0;
00118 wrdata_4d <= 0;
00119 wrdata_5d_half <= 0;
00120 wrmask_4d <= 0;
00121 wrmask_5d_half <= 0;
00122 end else begin
00123 wrdata_2d <= wrdata_1d;
00124 wrmask_2d <= wrmask_1d;
00125 wrdata_3d_half <= wrdata_2d[INTERFACE_DATA_WIDTH-1 : INTERFACE_DATA_WIDTH/2];
00126 wrmask_3d_half <= wrmask_2d[INTERFACE_MASK_WIDTH-1 : INTERFACE_MASK_WIDTH/2];
00127 wrdata_3d <= wrdata_2d;
00128 wrdata_4d_half <= wrdata_3d_half;
00129 wrmask_3d <= wrmask_2d;
00130 wrmask_4d_half <= wrmask_3d_half;
00131 wrdata_4d <= wrdata_3d;
00132 wrdata_5d_half <= wrdata_4d_half;
00133 wrmask_4d <= wrmask_3d;
00134 wrmask_5d_half <= wrmask_4d_half;
00135 end
00136 end
00137 assign dq_data_d0 = wrdata_4d[INTERFACE_DATA_WIDTH/2-1 : 0];
00138 assign dq_data_d1 = wrdata_5d_half;
00139 assign dq_data_ce = dqs_enable_4d_dq_clk90;
00140 assign dm_data_d0 = wrmask_4d[INTERFACE_MASK_WIDTH/2-1 : 0];
00141 assign dm_data_d1 = wrmask_5d_half;
00142 assign dm_data_ce = dqs_enable_4d_mask_clk90;
00143
00144
00145 always @ (posedge clk) begin :Dq_Enable_Reset
00146 integer k;
00147
00148 if (reset) begin
00149 dqs_enable_1d_dq <= 0;
00150 dqs_reset_1d_dq <= 0;
00151 end else begin
00152 dqs_reset_1d_dq <= {DDR2_DQS_DM_WIDTH{dqs_reset}};
00153 dqs_enable_1d_dq <= {DDR2_DQS_DM_WIDTH{dqs_enable}};
00154 end
00155 end
00156 always @ (posedge clk) begin :Dqs_Enable_Reset
00157 integer k;
00158
00159 if (reset) begin
00160 dqs_enable_1d <= 0;
00161 dqs_reset_1d <= 0;
00162 dqs_enable_2d <= 0;
00163 dqs_reset_2d <= 0;
00164 dqs_enable_3d <= 0;
00165 dqs_reset_3d <= 0;
00166 end else begin
00167 dqs_enable_1d <= {DDR2_DQS_DM_WIDTH{dqs_enable}};
00168 dqs_reset_1d <= {DDR2_DQS_DM_WIDTH{dqs_reset}};
00169 dqs_enable_2d <= dqs_enable_1d;
00170 dqs_reset_2d <= dqs_reset_1d;
00171 dqs_enable_3d <= dqs_enable_2d;
00172 dqs_reset_3d <= dqs_reset_2d;
00173 end
00174 end
00175
00176 always @ (posedge clk270) begin : Dqs_Loop
00177 integer k,m;
00178
00179 if (reset) begin
00180 dqs_enable_2d_dq <= 0;
00181 dqs_enable_2d_mask <= 0;
00182 dqs_reset_2d_dqtri <= 0;
00183 dqs_reset_2d_dq <= 0;
00184 dqs_enable_3d_dq <= 0;
00185 dqs_enable_3d_mask <= 0;
00186 dqs_reset_3d_dqtri <= 0;
00187 dqs_reset_3d_dq <= 0;
00188 dqs_enable_4d_dq <= 0;
00189 end else begin
00190 for (k=0; k<=DDR2_DATA_WIDTH-1; k=k+1) begin
00191 dqs_enable_2d_dq[k] <= dqs_enable_1d_dq[k/8];
00192 dqs_reset_2d_dqtri[k] <= dqs_reset_1d_dq[k/8];
00193 end
00194 dqs_enable_2d_mask <= dqs_enable_1d_dq;
00195 dqs_reset_2d_dq <= dqs_reset_1d_dq;
00196 dqs_enable_3d_dq <= dqs_enable_2d_dq;
00197 dqs_enable_3d_mask <= dqs_enable_2d_mask;
00198 dqs_reset_3d_dqtri <= dqs_reset_2d_dqtri;
00199 dqs_reset_3d_dq <= dqs_reset_2d_dq;
00200 dqs_enable_4d_dq <= dqs_enable_3d_dq;
00201 end
00202 end
00203 always @(posedge clk90) begin : Dqs_clk90_Loop
00204 if (reset) begin
00205 dqs_enable_4d_dq_clk90 <= 0;
00206 dqs_enable_4d_mask_clk90 <= 0;
00207 end else begin
00208 dqs_enable_4d_dq_clk90 <= dqs_enable_3d_dq;
00209 dqs_enable_4d_mask_clk90 <= dqs_enable_3d_mask;
00210 end
00211 end
00212
00213 assign dq_tri_d0 = ~dqs_enable_3d_dq;
00214 assign dq_tri_d1 = ~dqs_enable_4d_dq;
00215 assign dq_tri_ce = {DDR2_DATA_WIDTH{1'b1}}; // 常にイネーブル
00216 assign dqs_enable_node = dqs_enable_2d | dqs_enable_3d;
00217
00218 // ddr2_cont_iob.vのインスタンシエーション
00219 ddr2_cont_iob ddr2_cont_iob_inst(
00220 .clk90(clk90),
00221 .clk(clk),
00222 .reset(reset),
00223 .dq_data(dq_data),
00224 .dq_tri_d0(dq_tri_d0),
00225 .dq_tri_d1(dq_tri_d1),
00226 .dq_tri_ce(dq_tri_ce),
00227 .dq_data_d0(dq_data_d0),
00228 .dq_data_d1(dq_data_d1),
00229 .dq_data_ce(dq_data_ce),
00230 .dqs_reset(dqs_reset_2d),
00231 .dqs_enable(dqs_enable_node),
00232 .dqs_clk(dqs_clk),
00233 .dm_data_d0(dm_data_d0),
00234 .dm_data_d1(dm_data_d1),
00235 .dm_data_ce(dm_data_ce),
00236 .read_timing(read_timing),
00237 .read_timing_1b(read_timing_1b),
00238 .read_timing_2b(read_timing_2b),
00239 .fb_read_timing(fb_read_timing),
00240 .ddr2_dq(ddr2_dq),
00241 .ddr2_dqs(ddr2_dqs),
00242 .ddr2_dqs_n(ddr2_dqs_n),
00243 .ddr2_dm(ddr2_dm),
00244 .sd_loop_in(sd_loop_in),
00245 .sd_loop_out(sd_loop_out)
00246 );
00247
00248 // rddata_afifo.vのインスタンシエーション
00249 rddata_afifo rddata_afifo_inst(
00250 .clk(clk),
00251 .dqs_clk(dqs_clk),
00252 .reset(reset),
00253 .rd_en(rdd_afifo_rd_en),
00254 .wr_en(fb_read_timing),
00255 .din(dq_data),
00256 .dout(dout),
00257 .empty(rdd_afifo_empty),
00258 .almost_empty(rdd_afifo_almost_empty),
00259 .full(rdd_afifo_full),
00260 .almost_full(rdd_afifo_almost_full)
00261 );
00262
00263 // rdd_afifo_rd_enを生成する
00264 always @* begin
00265 if (rdd_afifo_empty) // emptyの時は読みださない
00266 rdd_afifo_rd_en <= 1'b0;
00267 else
00268 rdd_afifo_rd_en <= 1'b1;
00269 end
00270
00271 // valid_node、dout_nodeをラッチする
00272 always @(posedge clk) begin
00273 if (reset) begin
00274 valid_node <= 1'b0;
00275 dout_node <= 0;
00276 end else begin
00277 valid_node <= rdd_afifo_rd_en;
00278 dout_node <= dout;
00279 end
00280 end
00281 assign output_data = dout_node;
00282 assign rddata_valid = valid_node;
00283 endmodule
00284