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00002
00003
00004
00005 `default_nettype none
00006 `timescale 1ns / 1ps
00007
00008 module rddata_afifo(clk, dqs_clk, reset, din, dout, rd_en, wr_en, empty, almost_empty, full, almost_full);
00009 `include "./ddr2_cont_parameters.vh"
00010 input wire clk;
00011 input wire dqs_clk;
00012 input wire reset;
00013 input wire rd_en;
00014 input wire wr_en;
00015 input wire [DDR2_DATA_WIDTH-1 :0] din;
00016 output wire [INTERFACE_DATA_WIDTH-1 :0] dout;
00017 output wire empty;
00018 output wire almost_empty;
00019 output wire full;
00020 output wire almost_full;
00021
00022 wire empty_rise, empty_fall;
00023 wire almost_empty_rise, almost_empty_fall;
00024 wire full_rise, full_fall;
00025 wire almost_full_rise, almost_full_fall;
00026
00027
00028
00029 async_fifo_rise DQS2intclk_FIFO_RISE(
00030 .din (din[15:0]),
00031 .rd_clk (clk),
00032 .rst (reset),
00033 .rd_en (rd_en),
00034 .wr_en (wr_en),
00035 .wr_clk (dqs_clk),
00036 .almost_empty (almost_empty_rise),
00037 .almost_full (almost_full_rise),
00038 .dout (dout[15:0]),
00039 .empty (empty_rise),
00040 .full (full_rise)
00041 );
00042
00043
00044
00045 async_fifo_fall DQS2intclk_FIFO_FALL(
00046 .din (din[15:0]),
00047 .rd_clk (clk),
00048 .rst (reset),
00049 .rd_en (rd_en),
00050 .wr_en (wr_en),
00051 .wr_clk (dqs_clk),
00052 .almost_empty (almost_empty_fall),
00053 .almost_full (almost_full_fall),
00054 .dout (dout[31:16]),
00055 .empty (empty_fall),
00056 .full (full_fall)
00057 );
00058
00059
00060 assign empty = empty_rise | empty_fall;
00061 assign almost_empty = almost_empty_rise | almost_empty_fall;
00062 assign full = full_rise | full_fall;
00063 assign almost_full = almost_full_rise | almost_full_fall;
00064 endmodule
00065