関数 |
default_nettype none timescale
module | rddata_afifo (clk, dqs_clk, reset, din, dout, rd_en, wr_en, empty, almost_empty, full, almost_full) |
async_fifo_rise | DQS2intclk_FIFO_RISE (.din(din[15:0]),.rd_clk(clk),.rst(reset),.rd_en(rd_en),.wr_en(wr_en),.wr_clk(dqs_clk),.almost_empty(almost_empty_rise),.almost_full(almost_full_rise),.dout(dout[15:0]),.empty(empty_rise),.full(full_rise)) |
async_fifo_fall | DQS2intclk_FIFO_FALL (.din(din[15:0]),.rd_clk(clk),.rst(reset),.rd_en(rd_en),.wr_en(wr_en),.wr_clk(dqs_clk),.almost_empty(almost_empty_fall),.almost_full(almost_full_fall),.dout(dout[31:16]),.empty(empty_fall),.full(full_fall)) |
変数 |
include ddr2_cont_parameters
vh input wire | clk |
input wire | dqs_clk |
input wire | reset |
input wire | rd_en |
input wire | wr_en |
input wire[DDR2_DATA_WIDTH-1:0] | din |
output wire[INTERFACE_DATA_WIDTH-1:0] | dout |
output wire | empty = empty_rise | empty_fall |
output wire | almost_empty = almost_empty_rise | almost_empty_fall |
output wire | full = full_rise | full_fall |
output wire | almost_full = almost_full_rise | almost_full_fall |
wire | empty_rise |
wire | empty_fall |
wire | almost_empty_rise |
wire | almost_empty_fall |
wire | full_rise |
wire | full_fall |
wire | almost_full_rise |
wire | almost_full_fall |