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00008 `default_nettype none
00009 `timescale 1ns / 1ps
00010
00011 module ddr2_sdram_cont(sysclk, clk_out, reset, input_data, input_mask, read_write, output_data, input_address, addr_fifo_wren, wrdata_fifo_wren, addr_fifo_full, wrdata_fifo_full, rddata_valid, initialize_end, dcm_locked_in, dcm_locked_out, ddr2_clk, ddr2_clkb, ddr2_cke, ddr2_dqs, ddr2_dqs_n, ddr2_dq, ddr2_csb, ddr2_rasb, ddr2_casb, ddr2_web, ddr2_dm, ddr2_ba, ddr2_address, ddr2_odt, sd_loop_in, sd_loop_out);
00012 `include "./ddr2_cont_parameters.vh"
00013
00014 input wire sysclk;
00015 output wire clk_out;
00016 input wire reset;
00017 input wire [INTERFACE_DATA_WIDTH-1 : 0] input_data;
00018 input wire [INTERFACE_MASK_WIDTH-1 : 0] input_mask;
00019 input wire read_write;
00020 output wire [INTERFACE_DATA_WIDTH-1 : 0] output_data;
00021 input wire [USER_INPUT_ADDRESS_WIDTH-1 : 0] input_address;
00022 input wire addr_fifo_wren;
00023 input wire wrdata_fifo_wren;
00024 output reg addr_fifo_full;
00025 output reg wrdata_fifo_full;
00026 output wire rddata_valid;
00027 output wire initialize_end;
00028 input wire dcm_locked_in;
00029 output wire dcm_locked_out;
00030 output wire [QUANTITY_OF_CLK_OUTPUT-1 : 0] ddr2_clk;
00031 output wire [QUANTITY_OF_CLK_OUTPUT-1 : 0] ddr2_clkb;
00032 output wire ddr2_cke;
00033 inout wire [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dqs;
00034 inout wire [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dqs_n;
00035 inout wire [DDR2_DATA_WIDTH-1 : 0] ddr2_dq;
00036 output wire ddr2_csb;
00037 output wire ddr2_rasb;
00038 output wire ddr2_casb;
00039 output wire ddr2_web;
00040 output wire [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dm;
00041 output wire [1:0] ddr2_ba;
00042 output wire [DDR2_ADDRESS_WIDTH-1 : 0] ddr2_address;
00043 output wire ddr2_odt;
00044 input wire sd_loop_in;
00045 output wire sd_loop_out;
00046
00047 wire clk, clk90, clk1_16;
00048 wire [USER_INPUT_ADDRESS_WIDTH-1 : 0] address, next_address;
00049 wire read_writex, next_read_writex;
00050 wire addr_fifo_empty, addr_fifo_almost_empty, addr_fifo_rden;
00051 wire wrdata_fifo_empty, wrdata_fifo_almost_empty, wrdata_fifo_rden;
00052 wire dqs_enable, dqs_reset, write_timing, read_timing, burst_read;
00053 wire [INTERFACE_DATA_WIDTH-1 : 0] wrdata_fifo_data;
00054 wire [INTERFACE_MASK_WIDTH-1 : 0] wrdata_fifo_mask;
00055 wire wrdata_fifo_almost_full;
00056 wire dcm_locked_node;
00057 wire reset_node;
00058 wire addr_fifo_full_node, wrdata_fifo_full_node;
00059 wire addr_fifo_almost_full;
00060 wire read_timing_1b;
00061 wire read_timing_2b;
00062
00063 parameter AFIFO_IDLE = 3'b001,
00064 AFIFO_ALMOST_FULL = 3'b010,
00065 AFIFO_FULL = 3'b100;
00066 reg [2:0] afifo_cs, afifo_ns;
00067
00068 parameter WFIFO_IDLE = 3'b001,
00069 WFIFO_ALMOST_FULL = 3'b010,
00070 WFIFO_FULL = 3'b100;
00071 reg [2:0] wfifo_cs, wfifo_ns;
00072
00073 assign reset_node = reset | ~dcm_locked_node;
00074
00075 dcm_module dcm_module_inst(
00076 .sysclk(sysclk),
00077 .reset(reset_node),
00078 .ddr2_clk(ddr2_clk),
00079 .ddr2_clkb(ddr2_clkb),
00080 .clk(clk),
00081 .clk90(clk90),
00082 .clk1_16(clk1_16),
00083 .dcm_locked_in(dcm_locked_in),
00084 .dcm_locked_out(dcm_locked_node)
00085 );
00086 assign dcm_locked_out = dcm_locked_node;
00087
00088 controller controller_inst (
00089 .clk(clk),
00090 .clk1_16(clk1_16),
00091 .reset(reset_node),
00092 .address(address),
00093 .read_writex(read_writex),
00094 .next_address(next_address),
00095 .next_read_writex(next_read_writex),
00096 .addr_fifo_rden(addr_fifo_rden),
00097 .addr_fifo_empty(addr_fifo_empty),
00098 .addr_fifo_almost_empty(addr_fifo_almost_empty),
00099 .wrdata_fifo_empty(wrdata_fifo_empty),
00100 .wrdata_fifo_almost_empty(wrdata_fifo_almost_empty),
00101 .wrdata_fifo_rden(wrdata_fifo_rden),
00102 .ddr2_rasb(ddr2_rasb),
00103 .ddr2_casb(ddr2_casb),
00104 .ddr2_web(ddr2_web),
00105 .ddr2_ba(ddr2_ba),
00106 .ddr2_address(ddr2_address),
00107 .ddr2_cke(ddr2_cke),
00108 .ddr2_csb(ddr2_csb),
00109 .ddr2_odt(ddr2_odt),
00110 .dqs_enable(dqs_enable),
00111 .dqs_reset(dqs_reset),
00112 .write_timing(write_timing),
00113 .read_timing(read_timing),
00114 .read_timing_1b(read_timing_1b),
00115 .read_timing_2b(read_timing_2b),
00116 .burst_read(burst_read),
00117 .initialize_end(initialize_end)
00118 );
00119
00120 read_write_io read_write_io_inst (
00121 .reset(reset_node),
00122 .clk(clk),
00123 .clk90(clk90),
00124 .read_timing(read_timing),
00125 .read_timing_1b(read_timing_1b),
00126 .read_timing_2b(read_timing_2b),
00127 .burst_read(burst_read),
00128 .output_data(output_data),
00129 .rddata_valid(rddata_valid),
00130 .wrdata_fifo_data(wrdata_fifo_data),
00131 .wrdata_fifo_mask(wrdata_fifo_mask),
00132 .dqs_enable(dqs_enable),
00133 .dqs_reset(dqs_reset),
00134 .ddr2_dq(ddr2_dq),
00135 .ddr2_dqs(ddr2_dqs),
00136 .ddr2_dqs_n(ddr2_dqs_n),
00137 .ddr2_dm(ddr2_dm),
00138 .sd_loop_in(sd_loop_in),
00139 .sd_loop_out(sd_loop_out)
00140 );
00141
00142 addr_fifo addr_fifo_inst (
00143 .clk(clk),
00144 .reset(reset_node),
00145 .din(input_address),
00146 .read_write(read_write),
00147 .wr_en(addr_fifo_wren),
00148 .rd_en(addr_fifo_rden),
00149 .dout(address),
00150 .rw_out(read_writex),
00151 .full(addr_fifo_full_node),
00152 .empty(addr_fifo_empty),
00153 .next_dout(next_address),
00154 .next_rw_out(next_read_writex),
00155 .almost_empty(addr_fifo_almost_empty),
00156 .almost_full(addr_fifo_almost_full)
00157 );
00158
00159 wrdata_fifo wrdata_fifo_inst (
00160 .clk(clk),
00161 .reset(reset_node),
00162 .din(input_data),
00163 .maskin(input_mask),
00164 .rd_en(wrdata_fifo_rden),
00165 .wr_en(wrdata_fifo_wren),
00166 .full(wrdata_fifo_full_node),
00167 .almost_full(wrdata_fifo_almost_full),
00168 .empty(wrdata_fifo_empty),
00169 .almost_empty(wrdata_fifo_almost_empty),
00170 .dout(wrdata_fifo_data),
00171 .maskout(wrdata_fifo_mask)
00172 );
00173 assign clk_out = clk;
00174
00175
00176 always @(posedge clk) begin
00177 if (reset_node)
00178 afifo_cs <= AFIFO_IDLE;
00179 else
00180 afifo_cs <= afifo_ns;
00181 end
00182 always @* begin
00183 case(afifo_cs)
00184 AFIFO_IDLE : begin
00185 addr_fifo_full <= 1'b0;
00186 if (addr_fifo_almost_full)
00187 afifo_ns <= AFIFO_ALMOST_FULL;
00188 else
00189 afifo_ns <= AFIFO_IDLE;
00190 end
00191 AFIFO_ALMOST_FULL : begin
00192 addr_fifo_full <= 1'b1;
00193 if (addr_fifo_full_node)
00194 afifo_ns <= AFIFO_FULL;
00195 else if (~addr_fifo_almost_full)
00196 afifo_ns <= AFIFO_IDLE;
00197 else
00198 afifo_ns <= AFIFO_ALMOST_FULL;
00199 end
00200 AFIFO_FULL : begin
00201 addr_fifo_full <= 1'b1;
00202 if (~addr_fifo_full_node)
00203 afifo_ns <= AFIFO_ALMOST_FULL;
00204 else
00205 afifo_ns <= AFIFO_FULL;
00206 end
00207 endcase
00208 end
00209
00210
00211 always @(posedge clk) begin
00212 if (reset_node)
00213 wfifo_cs <= WFIFO_IDLE;
00214 else
00215 wfifo_cs <= wfifo_ns;
00216 end
00217 always @* begin
00218 case(wfifo_cs)
00219 WFIFO_IDLE : begin
00220 wrdata_fifo_full <= 1'b0;
00221 if (wrdata_fifo_almost_full)
00222 wfifo_ns <= WFIFO_ALMOST_FULL;
00223 else
00224 wfifo_ns <= WFIFO_IDLE;
00225 end
00226 WFIFO_ALMOST_FULL : begin
00227 wrdata_fifo_full <= 1'b1;
00228 if (wrdata_fifo_full_node)
00229 wfifo_ns <= WFIFO_FULL;
00230 else if (~wrdata_fifo_almost_full)
00231 wfifo_ns <= WFIFO_IDLE;
00232 else
00233 wfifo_ns <= WFIFO_ALMOST_FULL;
00234 end
00235 WFIFO_FULL : begin
00236 wrdata_fifo_full <= 1'b1;
00237 if (~wrdata_fifo_full_node)
00238 wfifo_ns <= WFIFO_ALMOST_FULL;
00239 else
00240 wfifo_ns <= WFIFO_FULL;
00241 end
00242 endcase
00243 end
00244
00245 endmodule