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00005
00006 `default_nettype none
00007 `timescale 1ns / 1ps
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00009
00010 module ddr2_cont_iob(clk90, clk, reset, dq_data, dq_tri_d0, dq_tri_d1, dq_tri_ce, dq_data_d0, dq_data_d1, dq_data_ce, dqs_reset, dqs_enable, dqs_clk, dm_data_d0, dm_data_d1, dm_data_ce, read_timing, read_timing_1b, read_timing_2b, fb_read_timing, ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_dm, sd_loop_in, sd_loop_out);
00011 `include "./ddr2_cont_parameters.vh"
00012 input wire clk90;
00013 input wire clk;
00014 input wire reset;
00015 output wire [DDR2_DATA_WIDTH-1: 0] dq_data;
00016 input wire [DDR2_DATA_WIDTH-1: 0] dq_tri_d0;
00017 input wire [DDR2_DATA_WIDTH-1: 0] dq_tri_d1;
00018 input wire [DDR2_DATA_WIDTH-1: 0] dq_tri_ce;
00019 input wire [DDR2_DATA_WIDTH-1: 0] dq_data_d0;
00020 input wire [DDR2_DATA_WIDTH-1: 0] dq_data_d1;
00021 input wire [DDR2_DATA_WIDTH-1: 0] dq_data_ce;
00022 input wire [DDR2_DQS_DM_WIDTH-1: 0] dqs_reset;
00023 input wire [DDR2_DQS_DM_WIDTH-1: 0] dqs_enable;
00024 output wire dqs_clk;
00025 input wire [DDR2_DQS_DM_WIDTH-1: 0] dm_data_d0;
00026 input wire [DDR2_DQS_DM_WIDTH-1: 0] dm_data_d1;
00027 input wire [DDR2_DQS_DM_WIDTH-1: 0] dm_data_ce;
00028 input wire read_timing;
00029 input wire read_timing_1b;
00030 input wire read_timing_2b;
00031 output wire fb_read_timing;
00032
00033 inout wire [DDR2_DATA_WIDTH-1: 0] ddr2_dq;
00034 inout wire [DDR2_DQS_DM_WIDTH-1: 0] ddr2_dqs;
00035 inout wire [DDR2_DQS_DM_WIDTH-1: 0] ddr2_dqs_n;
00036 output wire [DDR2_DQS_DM_WIDTH-1: 0] ddr2_dm;
00037 input wire sd_loop_in;
00038 (* IOB = "FORCE" *)output reg sd_loop_out;
00039
00040 wire [DDR2_DQS_DM_WIDTH-1: 0] dqs_clk_node;
00041 wire dqs_clk_bufg;
00042
00043 generate
00044 genvar i;
00045 for (i=DDR2_DATA_WIDTH-1; i>=0; i=i-1) begin: DQ_IOB_INST
00046 dq_io_pad dq_io_pad_inst(
00047 .input_clk(dqs_clk_bufg),
00048 .clk(clk),
00049 .clk90(clk90),
00050 .reset(reset),
00051 .io_pad(ddr2_dq[i]),
00052 .dq_data_from_io(dq_data[i]),
00053 .tri_ddr_ce_to_io(dq_tri_ce[i]),
00054 .tri_ddr_d0_to_io(dq_tri_d0[i]),
00055 .tri_ddr_d1_to_io(dq_tri_d1[i]),
00056 .data_ddr_ce_to_io(dq_data_ce[i]),
00057 .data_ddr_d0_to_io(dq_data_d0[i]),
00058 .data_ddr_d1_to_io(dq_data_d1[i])
00059 );
00060 end
00061 endgenerate
00062
00063 generate
00064 genvar j;
00065 for (j=DDR2_DQS_DM_WIDTH-1; j>=0; j=j-1) begin: DQS_IOB_INST
00066 dqs_io_pad dqs_io_pad_inst(
00067 .clk(clk),
00068 .reset(reset),
00069 .io_pad(ddr2_dqs[j]),
00070 .dqs_reset(dqs_reset[j]),
00071 .dqs_enable(dqs_enable[j]),
00072 .dqs_clk(dqs_clk_node[j])
00073 );
00074 end
00075 endgenerate
00076
00077 generate
00078 genvar k;
00079 for (k=DDR2_DQS_DM_WIDTH-1; k>=0; k=k-1) begin: DQSB_IOB_INST
00080 dqsb_io_pad dqsb_io_pad_inst(
00081 .clk(clk),
00082 .reset(reset),
00083 .io_pad(ddr2_dqs_n[k]),
00084 .dqs_reset(dqs_reset[k]),
00085 .dqs_enable(dqs_enable[k]),
00086 .dqs_clk()
00087 );
00088 end
00089 endgenerate
00090
00091 BUFG BUFG_inst(
00092 .O(dqs_clk_bufg),
00093 .I(dqs_clk_node[0])
00094 );
00095 assign dqs_clk = dqs_clk_bufg;
00096
00097 generate
00098 genvar m;
00099 for (m=DDR2_DQS_DM_WIDTH-1; m>=0; m=m-1) begin: DM_IOB_INST
00100 dm_io_pad dm_io_pad_inst(
00101 .clk90(clk90),
00102 .reset(reset),
00103 .io_pad(ddr2_dm[m]),
00104 .data_ddr_ce_to_io(dm_data_ce[m]),
00105 .data_ddr_d0_to_io(dm_data_d0[m]),
00106 .data_ddr_d1_to_io(dm_data_d1[m])
00107 );
00108 end
00109 endgenerate
00110
00111 always @ (posedge clk) begin
00112 if (reset)
00113 sd_loop_out = 1'b0;
00114 else begin
00115 sd_loop_out = read_timing_1b;
00116 end
00117 end
00118
00119 assign fb_read_timing = sd_loop_in;
00120 endmodule
00121