関数 |
default_nettype none timescale
module | ddr2_cont_iob (clk90, clk, reset, dq_data, dq_tri_d0, dq_tri_d1, dq_tri_ce, dq_data_d0, dq_data_d1, dq_data_ce, dqs_reset, dqs_enable, dqs_clk, dm_data_d0, dm_data_d1, dm_data_ce, read_timing, read_timing_1b, read_timing_2b, fb_read_timing, ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_dm, sd_loop_in, sd_loop_out) |
for(k=DDR2_DQS_DM_WIDTH-1;k >
=0;k=k-1) begin end
endgenerate BUFG | BUFG_inst (.O(dqs_clk_bufg),.I(dqs_clk_node[0])) |
for(m=DDR2_DQS_DM_WIDTH-1;m >
=0;m=m-1) begin end
endgenerate | always (posedge clk) begin if(reset) sd_loop_out |
変数 |
include ddr2_cont_parameters
vh input wire | clk90 |
input wire | clk |
input wire | reset |
output wire[DDR2_DATA_WIDTH-1:0] | dq_data |
input wire[DDR2_DATA_WIDTH-1:0] | dq_tri_d0 |
input wire[DDR2_DATA_WIDTH-1:0] | dq_tri_d1 |
input wire[DDR2_DATA_WIDTH-1:0] | dq_tri_ce |
input wire[DDR2_DATA_WIDTH-1:0] | dq_data_d0 |
input wire[DDR2_DATA_WIDTH-1:0] | dq_data_d1 |
input wire[DDR2_DATA_WIDTH-1:0] | dq_data_ce |
input wire[DDR2_DQS_DM_WIDTH-1:0] | dqs_reset |
input wire[DDR2_DQS_DM_WIDTH-1:0] | dqs_enable |
output wire | dqs_clk = dqs_clk_bufg |
input wire[DDR2_DQS_DM_WIDTH-1:0] | dm_data_d0 |
input wire[DDR2_DQS_DM_WIDTH-1:0] | dm_data_d1 |
input wire[DDR2_DQS_DM_WIDTH-1:0] | dm_data_ce |
input wire | read_timing |
input wire | read_timing_1b |
input wire | read_timing_2b |
output wire | fb_read_timing = sd_loop_in |
inout wire[DDR2_DATA_WIDTH-1:0] | ddr2_dq |
inout wire[DDR2_DQS_DM_WIDTH-1:0] | ddr2_dqs |
inout wire[DDR2_DQS_DM_WIDTH-1:0] | ddr2_dqs_n |
output wire[DDR2_DQS_DM_WIDTH-1:0] | ddr2_dm |
input wire | sd_loop_in |
IOB output reg | sd_loop_out = read_timing_1b |
wire[DDR2_DQS_DM_WIDTH-1:0] | dqs_clk_node |
wire | dqs_clk_bufg |
generate genvar | i |
for(i=DDR2_DATA_WIDTH-1;i >
=0;i=i-1) begin end
endgenerate generate genvar | j |
for(j=DDR2_DQS_DM_WIDTH-1;j >
=0;j=j-1) begin end
endgenerate generate genvar | k |
generate genvar | m |