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00014 `default_nettype none
00015 `timescale 1ns / 1ps
00016
00017
00018
00019 module controller(clk, clk1_16, reset, address, read_writex, next_address, next_read_writex, addr_fifo_empty, addr_fifo_almost_empty, addr_fifo_rden, wrdata_fifo_empty, wrdata_fifo_almost_empty, wrdata_fifo_rden, ddr2_rasb, ddr2_casb, ddr2_web, ddr2_ba, ddr2_address, ddr2_cke, ddr2_csb, ddr2_odt, dqs_enable, dqs_reset, write_timing, read_timing, read_timing_1b, read_timing_2b, burst_read, initialize_end);
00020 `include "./ddr2_cont_parameters.vh"
00021
00022 input clk, clk1_16, reset;
00023 input [USER_INPUT_ADDRESS_WIDTH-1:0] address;
00024 input read_writex;
00025 input [USER_INPUT_ADDRESS_WIDTH-1:0] next_address;
00026 input next_read_writex;
00027 input addr_fifo_empty, addr_fifo_almost_empty;
00028 output addr_fifo_rden;
00029 input wrdata_fifo_empty, wrdata_fifo_almost_empty;
00030 output wrdata_fifo_rden;
00031 output ddr2_rasb, ddr2_casb, ddr2_web;
00032 output [1:0] ddr2_ba;
00033 output [DDR2_ADDRESS_WIDTH-1:0] ddr2_address;
00034 output ddr2_cke, ddr2_csb, ddr2_odt, dqs_enable, dqs_reset;
00035 output write_timing, read_timing, burst_read;
00036 output read_timing_1b;
00037 output read_timing_2b;
00038 output initialize_end;
00039
00040 wire clk, clk1_16, reset;
00041 wire [USER_INPUT_ADDRESS_WIDTH-1:0] address;
00042 wire read_writex;
00043 wire [USER_INPUT_ADDRESS_WIDTH-1:0] next_address;
00044 wire next_read_writex;
00045 wire addr_fifo_empty, addr_fifo_almost_empty;
00046 wire addr_fifo_rden;
00047 wire wrdata_fifo_empty, wrdata_fifo_almost_empty;
00048 wire wrdata_fifo_rden;
00049 wire ddr2_rasb, ddr2_casb, ddr2_web;
00050 wire [1:0] ddr2_ba;
00051 wire [DDR2_ADDRESS_WIDTH-1:0] ddr2_address;
00052 reg ddr2_cke, dqs_enable;
00053 wire ddr2_csb;
00054 reg dqs_reset;
00055 wire write_timing, read_timing, burst_read;
00056 wire read_timing_1b;
00057 wire read_timing_2b;
00058 reg initialize_end;
00059
00060 wire clkx;
00061 wire [DDR2_ADDRESS_WIDTH-1:0] row_addr, next_row_addr;
00062 reg [DDR2_COLUMN_ADDRESS_WIDTH-1:0] column_addr;
00063 wire [1:0] bank_addr, next_bank_addr;
00064 reg [1:0] TRP;
00065 reg [1:0] TMRD;
00066 reg [1:0] TRCD;
00067 reg [2:0] TPAR;
00068 reg [2:0] TRTW;
00069 reg [2:0] TPAW;
00070 reg [2:0] TWTR;
00071 reg [3:0] TRFC;
00072 reg [3:0] TRC;
00073 reg [2:0] TRAS;
00074 reg [1:0] TRTR, TWTW;
00075 reg [11:0] initial_count;
00076 reg initial_start, initial_startx;
00077 reg read_cmd_issue, read_cmd_issue_1d;
00078
00079 parameter idle_init= 14'b00000000000001,
00080 pall1_init= 14'b00000000000010,
00081 emr2s_init= 14'b00000000000100,
00082 emr3s_init= 14'b00000000001000,
00083 emrs_dllena_init= 14'b00000000010000,
00084 mrs_dllrst_init= 14'b00000000100000,
00085 pall2_init= 14'b00000001000000,
00086 ref1_init= 14'b00000010000000,
00087 ref2_init= 14'b00000100000000,
00088 mrs_init= 14'b00001000000000,
00089 emrs_ocd_def_init= 14'b00010000000000,
00090 emrs_ocd_exit_init= 14'b00100000000000,
00091 wait_init_end= 14'b01000000000000,
00092 init_end= 14'b10000000000000;
00093
00094 parameter NOP= 8'b00000001,
00095 ACT= 8'b00000010,
00096 READ= 8'b00000100,
00097 WRIT= 8'b00001000,
00098 PALL= 8'b00010000,
00099 MRS= 8'b00100000,
00100 EMRS= 8'b01000000,
00101 REF= 8'b10000000;
00102
00103 parameter IDLE_ODT= 4'b0001,
00104 WRITE_ACTIVE= 4'b0010,
00105 WRITE_TEST= 4'b0100,
00106 WRITE_HOLDOFF1= 4'b1000;
00107
00108 reg [13:0] n_init, c_init;
00109 reg [7:0] n_state, c_state, b_state, b2_state;
00110
00111 parameter idle_dets= 3'b001,
00112 write_dets= 3'b010,
00113 write_wait= 3'b100;
00114
00115 reg [2:0] ns_dets, cs_dets; // idle_dets
00116
00117 reg cke_stat;
00118 reg [USER_INPUT_ADDRESS_WIDTH-3 : USER_INPUT_ADDRESS_WIDTH-3-(DDR2_ADDRESS_WIDTH-1)] active_row_addr;
00119 reg [USER_INPUT_ADDRESS_WIDTH-1 : USER_INPUT_ADDRESS_WIDTH-2] active_bank_addr;
00120 wire ref_state;
00121 reg ref_then_by_now;
00122 wire ref_req;
00123 reg [MAX_REFRESH_COUNT_LENGTH-1 : 0] ref_count;
00124 wire equal_active_bank, equal_active_bank_next;
00125 reg equal_active_bank_1d, addr_fifo_empty_1d, addr_fifo_almost_empty_1d;
00126 reg read_writex_1d, next_read_writex_1d;
00127 reg equal_active_bank_next_1d, equal_active_bank_next_2d;
00128 reg activate_bank;
00129 reg [DDR2_ADDRESS_WIDTH-1 :0] ddr2_addr_node, ddr2_addr_node_1d, ddr2_addr_node_2d;
00130 reg [1:0] bank_addr_node, bank_addr_node_1d, bank_addr_node_2d;
00131 reg [DDR2_ADDRESS_WIDTH-1 :0] ddr2_addr_node_3d;
00132 reg [1:0] bank_addr_node_3d;
00133 reg rasb_node, casb_node, web_node;
00134 reg rasb_node_1d, casb_node_1d, web_node_1d;
00135 reg rasb_node_2d, casb_node_2d, web_node_2d;
00136 reg rasb_node_3d, casb_node_3d, web_node_3d;
00137 wire wrdata_fifo_rden_node;
00138 reg [4:0] dll_reset_cnt;
00139 reg dll_reset_end, dll_reset_flag;
00140 reg before_cmd_is_ACT;
00141 reg [CAS_LATENCY :0] read_timing_node;
00142 reg [CLK2PALLA_CNT_WIDTH-1 :0] cke2palla_cnt;
00143 reg cke2palla_ena;
00144 reg [3:0] ns_odt, cs_odt;
00145 reg odt_node, odt_node_1d;
00146 reg cke_stat_clk0;
00147
00148 assign ddr2_csb = 1'b0;
00149 assign clkx = ~clk;
00150
00151 assign row_addr = address[USER_INPUT_ADDRESS_WIDTH-3 : USER_INPUT_ADDRESS_WIDTH-3-(DDR2_ADDRESS_WIDTH-1)];
00152 always @(posedge clk) begin
00153 if (reset==1'b1)
00154 column_addr <= 0;
00155 else
00156 column_addr <= address[DDR2_COLUMN_ADDRESS_WIDTH-1 :0];
00157 end
00158 assign bank_addr = address[USER_INPUT_ADDRESS_WIDTH-1 : USER_INPUT_ADDRESS_WIDTH-2];
00159 assign next_row_addr = next_address[USER_INPUT_ADDRESS_WIDTH-3 : USER_INPUT_ADDRESS_WIDTH-3-(DDR2_ADDRESS_WIDTH-1)];
00160 assign next_bank_addr = next_address[USER_INPUT_ADDRESS_WIDTH-1 : USER_INPUT_ADDRESS_WIDTH-2];
00161
00162 // 現在アクティブなバンク、Rowアドレスをラッチしておく
00163 always @(posedge clk) begin
00164 if (reset) begin
00165 active_row_addr <= 0;
00166 active_bank_addr <= 0;
00167 end else if (c_state==ACT) begin // DDR2 SDRAMをアクティベートする時
00168 active_row_addr <= row_addr;
00169 active_bank_addr <= bank_addr;
00170 end
00171 end
00172 assign equal_active_bank = (active_row_addr==row_addr && active_bank_addr==bank_addr) ? 1'b1 : 1'b0;
00173 assign equal_active_bank_next = (active_row_addr==next_row_addr && active_bank_addr==next_bank_addr) ? 1'b1 : 1'b0;
00174
00175 always @(posedge clk) begin // 以前のコマンドはACTコマンド、ACTコマンドの次のWRIT、READコマンドの時は、同一バンク、ROWアドレスチェックを回避するため
00176 if (reset)
00177 before_cmd_is_ACT <= 1'b0;
00178 else if (c_state == ACT)
00179 before_cmd_is_ACT <= 1'b1;
00180 // else if (n_state != NOP) // 次の判定に影響を及ぼさないように、1クロック早める
00181 else if (c_state != NOP) // ddr2ではREAD, WRITEの後に必ずNOPが入る
00182 before_cmd_is_ACT <= 1'b0;
00183 end
00184
00185 always @(posedge clk) begin
00186 if (reset)
00187 activate_bank <= 1'b0;
00188 else if (c_state == ACT)
00189 activate_bank <= 1'b1;
00190 else if (c_state == PALL)
00191 activate_bank <= 1'b0;
00192 end
00193
00194 always @(posedge clk) begin
00195 if (reset) begin
00196 equal_active_bank_1d <= 1'b0;
00197 addr_fifo_empty_1d <= 1'b0;
00198 addr_fifo_almost_empty_1d <= 1'b0;
00199 read_writex_1d <= 1'b0;
00200 equal_active_bank_next_1d <= 1'b0;
00201 equal_active_bank_next_2d <= 1'b0;
00202 next_read_writex_1d <= 1'b0;
00203 end else begin
00204 equal_active_bank_1d <= equal_active_bank;
00205 addr_fifo_empty_1d <= addr_fifo_empty;
00206 addr_fifo_almost_empty_1d <= addr_fifo_almost_empty;
00207 read_writex_1d <= read_writex;
00208 equal_active_bank_next_1d <= equal_active_bank_next;
00209 equal_active_bank_next_2d <= equal_active_bank_next_1d;
00210 next_read_writex_1d <= next_read_writex;
00211 end
00212 end
00213
00214
00215
00216 always @(posedge clk) begin
00217 if (reset)
00218 TRP <= 0;
00219 else if (c_state==PALL)
00220 TRP <= 1;
00221 else if (TRP != 0)
00222 TRP <= TRP - 1;
00223 end
00224
00225
00226 always @(posedge clk) begin
00227 if (reset)
00228 TMRD <= 0;
00229 else if (c_state==MRS || c_state==EMRS)
00230 TMRD <= 1;
00231 else if (TMRD != 0)
00232 TMRD <= TMRD - 1;
00233 end
00234
00235
00236 always @(posedge clk) begin
00237 if (reset)
00238 TRFC <= 0;
00239 else if (c_state==REF)
00240 TRFC <= 14;
00241 else if (TRFC != 0)
00242 TRFC <= TRFC - 1;
00243 end
00244
00245
00246 always @(posedge clk) begin
00247 if (reset)
00248 TRCD <= 0;
00249 else if (c_state==ACT)
00250 TRCD <= 1;
00251 else if (TRCD != 0)
00252 TRCD <= TRCD - 1;
00253 end
00254
00255
00256 always @(posedge clk) begin
00257 if (reset)
00258 TRAS <= 0;
00259 else if (c_state==ACT)
00260 TRAS <= 6;
00261 else if (TRAS != 0)
00262 TRAS <= TRAS - 1;
00263 end
00264
00265
00266 always @(posedge clk) begin
00267 if (reset)
00268 TRC <= 0;
00269 else if (c_state==REF)
00270 TRC <= 9;
00271 else if (TRC != 0)
00272 TRC <= TRC - 1;
00273 end
00274
00275
00276 always @(posedge clk) begin
00277 if (reset)
00278 TPAW <= 0;
00279 else if (c_state==WRIT)
00280 TPAW <= 5;
00281 else if (TPAW != 0)
00282 TPAW <= TPAW - 1;
00283 end
00284
00285
00286 always @(posedge clk) begin
00287 if (reset)
00288 TPAR <= 0;
00289 else if (c_state==READ)
00290 TPAR <= 1;
00291 else if (TPAR != 0)
00292 TPAR <= TPAR - 1;
00293 end
00294
00295
00296
00297 always @(posedge clk) begin
00298 if (reset)
00299 TRTW <= 0;
00300 else if (c_state==READ)
00301 TRTW <= 4;
00302 else if (TRTW != 0)
00303 TRTW <= TRTW - 1;
00304 end
00305
00306
00307 always @(posedge clk) begin
00308 if (reset)
00309 TWTR <= 0;
00310 else if (c_state==WRIT)
00311 TWTR <= 4;
00312 else if (TWTR != 0)
00313 TWTR <= TWTR - 1;
00314 end
00315
00316
00317 always @(posedge clk) begin
00318 if (reset)
00319 TRTR <= 0;
00320 else if (c_state==READ)
00321 TRTR <= 1;
00322 else if (TRTR != 0)
00323 TRTR <= TRTR - 1;
00324 end
00325
00326
00327 always @(posedge clk) begin
00328 if (reset)
00329 TWTW <= 0;
00330 else if (c_state==WRIT)
00331 TWTW <= 1;
00332 else if (TWTW != 0)
00333 TWTW <= TWTW - 1;
00334 end
00335
00336
00337 always @(posedge clk1_16) begin
00338 if (reset) begin
00339 initial_count <= 0;
00340 initial_start <= 1'b0;
00341 end else if (initial_count != MAX_INITIAL_COUNT_VAL)
00342 initial_count <= initial_count + 1;
00343 else if (initial_count==MAX_INITIAL_COUNT_VAL)
00344 initial_start <= 1'b1;
00345 end
00346
00347 always @(posedge clk) begin
00348 if (reset)
00349 initial_startx <= 1'b0;
00350 else
00351 initial_startx <= initial_start;
00352 end
00353
00354
00355 always @(posedge clk) begin
00356 if (reset)
00357 cke_stat_clk0 <= 1'b0;
00358 else
00359 cke_stat_clk0 <= cke_stat;
00360 end
00361
00362
00363 always @(posedge clkx, posedge reset) begin
00364 if (reset) begin
00365 cke_stat <= 1'b0;
00366 ddr2_cke <= 1'b0;
00367 end else begin
00368 if (initial_startx==1'b1)
00369 cke_stat <= 1'b1;
00370
00371 ddr2_cke <= cke_stat;
00372 end
00373 end
00374
00375
00376 always @(posedge clk) begin
00377 if (reset) begin
00378 cke2palla_cnt <= 0;
00379 cke2palla_ena <= 1'b0;
00380 end else if (!cke2palla_ena && initial_startx && cke_stat_clk0) begin
00381
00382 if (cke2palla_cnt == CLK2PALLA_CNT_VAL)
00383 cke2palla_ena <= 1'b1;
00384 else
00385 cke2palla_cnt <= cke2palla_cnt + 1;
00386 end
00387 end
00388
00389
00390 always @(posedge clk) begin
00391 if (reset)
00392 dll_reset_flag <= 1'b0;
00393 else if (c_init==mrs_dllrst_init && c_state==MRS)
00394 dll_reset_flag <= 1'b1;
00395 end
00396
00397 always @(posedge clk1_16) begin
00398 if (reset)
00399 dll_reset_cnt <= 0;
00400 else if (dll_reset_cnt[4]==1'b0 && dll_reset_flag==1'b1)
00401 dll_reset_cnt <= dll_reset_cnt + 1;
00402 end
00403
00404
00405 always @(posedge clk) begin
00406 if (reset)
00407 dll_reset_end <= 1'b0;
00408 else
00409 dll_reset_end <= dll_reset_cnt[4];
00410 end
00411
00412
00413 always @(posedge clk1_16) begin
00414 if (reset)
00415 ref_count <= 0;
00416 else if (ref_count==MAX_REFRESH_COUNT)
00417 ref_count <= 0;
00418 else
00419 ref_count <= ref_count + 1;
00420 end
00421
00422 always @(posedge clk) begin
00423 if (reset)
00424 ref_then_by_now <= 1'b0;
00425 else
00426 ref_then_by_now <= ref_count[MAX_REFRESH_COUNT_LENGTH-1];
00427 end
00428
00429 refreqsm REF_REQ_SM (
00430 .CLK(clk),
00431 .RESET(reset),
00432 .ref_state(ref_state),
00433 .ref_then_by_now(ref_then_by_now),
00434 .ref_req(ref_req)
00435 );
00436 assign ref_state = (c_state==REF) ? 1'b1 : 1'b0;
00437
00438
00439 always @(posedge clk) begin
00440 if (reset)
00441 c_init <= idle_init;
00442 else
00443 c_init <= n_init;
00444 end
00445
00446 always @ * begin
00447 case (c_init)
00448 idle_init :
00449 if (initial_startx && cke_stat && cke2palla_ena)
00450 n_init <= pall1_init;
00451 else
00452 n_init <= idle_init;
00453 pall1_init :
00454 if (c_state==PALL)
00455 n_init <= emr2s_init;
00456 else
00457 n_init <= pall1_init;
00458 emr2s_init :
00459 if (c_state==EMRS)
00460 n_init <= emr3s_init;
00461 else
00462 n_init <= emr2s_init;
00463 emr3s_init :
00464 if (c_state==EMRS)
00465 n_init <= emrs_dllena_init;
00466 else
00467 n_init <= emr3s_init;
00468 emrs_dllena_init :
00469 if (c_state==EMRS)
00470 n_init <= mrs_dllrst_init;
00471 else
00472 n_init <= emrs_dllena_init;
00473 mrs_dllrst_init :
00474 if (c_state==MRS)
00475 n_init <= pall2_init;
00476 else
00477 n_init <= mrs_dllrst_init;
00478 pall2_init :
00479 if (c_state==PALL)
00480 n_init <= ref1_init;
00481 else
00482 n_init <= pall2_init;
00483 ref1_init :
00484 if (c_state==REF)
00485 n_init <= ref2_init;
00486 else
00487 n_init <= ref1_init;
00488 ref2_init :
00489 if (c_state==REF)
00490 n_init <= mrs_init;
00491 else
00492 n_init <= ref2_init;
00493 mrs_init :
00494 if (c_state==MRS)
00495 n_init <= emrs_ocd_def_init;
00496 else
00497 n_init <= mrs_init;
00498 emrs_ocd_def_init :
00499 if (c_state==EMRS)
00500 n_init <= emrs_ocd_exit_init;
00501 else
00502 n_init <= emrs_ocd_def_init;
00503 emrs_ocd_exit_init :
00504 if (c_state==EMRS)
00505 n_init <= wait_init_end;
00506 else
00507 n_init <= emrs_ocd_exit_init;
00508 wait_init_end :
00509 if (TMRD==0 && dll_reset_end==1'b1)
00510
00511 n_init <= init_end;
00512 else
00513 n_init <= wait_init_end;
00514 init_end :
00515 n_init <= init_end;
00516 endcase
00517 end
00518
00519
00520 always @(posedge clk) begin
00521 if (reset)
00522 c_state <= NOP;
00523 else
00524 c_state <= n_state;
00525 end
00526
00527 always @ * begin
00528 case (c_state)
00529 NOP : begin
00530 if (c_init != init_end) begin
00531 case (c_init)
00532 pall1_init :
00533 n_state <= PALL;
00534 emr2s_init :
00535 if (TRP==0)
00536 n_state <= EMRS;
00537 else
00538 n_state <= NOP;
00539 emr3s_init :
00540 if (TMRD==0)
00541 n_state <= EMRS;
00542 else
00543 n_state <= NOP;
00544 emrs_dllena_init :
00545 if (TMRD==0)
00546 n_state <= EMRS;
00547 else
00548 n_state <= NOP;
00549 mrs_dllrst_init :
00550 if (TMRD==0)
00551 n_state <= MRS;
00552 else
00553 n_state <= NOP;
00554 pall2_init :
00555 if (TMRD==0)
00556 n_state <= PALL;
00557 else
00558 n_state <= NOP;
00559 ref1_init :
00560 if (TRP==0)
00561 n_state <= REF;
00562 else
00563 n_state <= NOP;
00564 ref2_init :
00565 if (TRFC==0)
00566 n_state <= REF;
00567 else
00568 n_state <= NOP;
00569 mrs_init :
00570 if (TRFC==0)
00571 n_state <= MRS;
00572 else
00573 n_state <= NOP;
00574 emrs_ocd_def_init :
00575 if (TMRD==0)
00576 n_state <= EMRS;
00577 else
00578 n_state <= NOP;
00579 emrs_ocd_exit_init :
00580 if (TMRD==0)
00581 n_state <= EMRS;
00582 else
00583 n_state <= NOP;
00584 default :
00585 n_state <= NOP;
00586 endcase
00587 end else begin
00588 if (ref_req==1'b1) begin
00589 if (activate_bank==1'b1) begin
00590 if (TRAS==0 && TPAW==0 && TPAR==0)
00591 n_state <= PALL;
00592 else
00593 n_state <= NOP;
00594 end else
00595 if (TRP==0)
00596 n_state <= REF;
00597 else
00598 n_state <= NOP;
00599 end else if (addr_fifo_empty==1'b0 && activate_bank==1'b0 && TRP==0 && TRFC==0 && TRC==0)
00600 n_state <= ACT;
00601 else if (activate_bank==1'b1 && addr_fifo_empty==1'b0 && read_writex==1'b1) begin
00602 if ((equal_active_bank_next_2d & equal_active_bank_1d) || before_cmd_is_ACT==1'b1) begin
00603 if (TWTR==0 && TRCD==0)
00604 n_state <= READ;
00605 else
00606 n_state <= NOP;
00607 end else begin
00608 if (TRAS==0 && TPAW==0 && TPAR==0)
00609 n_state <= PALL;
00610 else
00611 n_state <= NOP;
00612 end
00613 end else if (activate_bank==1'b1 && addr_fifo_empty==1'b0 && read_writex==1'b0) begin
00614 if (equal_active_bank || before_cmd_is_ACT==1'b1) begin
00615 if (TRTW==0 && TRCD==0)
00616 n_state <= WRIT;
00617 else
00618 n_state <= NOP;
00619 end else begin
00620 if (TRAS==0 && TPAW==0 && TPAR==0)
00621 n_state <= PALL;
00622 else
00623 n_state <= NOP;
00624 end
00625 end else
00626 n_state <= NOP;
00627 end
00628 end
00629 REF : n_state <= NOP;
00630 PALL : n_state <= NOP;
00631 MRS : n_state <= NOP;
00632 EMRS : n_state <= NOP;
00633 ACT : n_state <= NOP;
00634 READ : begin
00635 n_state <= NOP;
00636 end
00637 WRIT : begin
00638 n_state <= NOP;
00639 end
00640 default: n_state <= NOP;
00641 endcase
00642 end
00643
00644 assign addr_fifo_rden = (c_init==init_end && !addr_fifo_empty && (c_state==READ || c_state==WRIT)) ? 1'b1 : 1'b0;
00645 assign wrdata_fifo_rden_node = (c_state==WRIT || b_state==WRIT) ? 1'b1 : 1'b0;
00646
00647 assign wrdata_fifo_rden = wrdata_fifo_rden_node;
00648
00649
00650 always @ (posedge clk) begin
00651 if (reset)
00652 ;
00653 else
00654 if (wrdata_fifo_rden && wrdata_fifo_empty) begin
00655 $display("%m: at time %t ERROR : wrdata_fifoをリードしたときにwrdata_fifoは空だった。DDR2 SDRAMコントローラでDDR2にライトする場合は、1つアドレスを書く毎に2つのデータを書き込む必要がある",$time);
00656 $stop;
00657 end
00658 end
00659
00660
00661 always @ * begin
00662 case (c_state)
00663 READ : begin rasb_node <= 1'b1; casb_node <= 1'b0; web_node <= 1'b1;
00664 end
00665 WRIT : begin rasb_node <= 1'b1; casb_node <= 1'b0; web_node <= 1'b0;
00666 end
00667 ACT : begin rasb_node <= 1'b0; casb_node <= 1'b1; web_node <= 1'b1;
00668 end
00669 PALL : begin rasb_node <= 1'b0; casb_node <= 1'b1; web_node <= 1'b0;
00670 end
00671 MRS : begin rasb_node <= 1'b0; casb_node <= 1'b0; web_node <= 1'b0;
00672 end
00673 EMRS : begin rasb_node <= 1'b0; casb_node <= 1'b0; web_node <= 1'b0;
00674 end
00675 REF : begin rasb_node <= 1'b0; casb_node <= 1'b0; web_node <= 1'b1;
00676 end
00677 default : begin rasb_node <= 1'b1; casb_node <= 1'b1; web_node <= 1'b1;
00678 end
00679 endcase
00680 end
00681
00682 always @(posedge clk) begin
00683 if (reset) begin
00684 rasb_node_1d <= 1'b1;
00685 casb_node_1d <= 1'b1;
00686 web_node_1d <= 1'b1;
00687 end else begin
00688 rasb_node_1d <= rasb_node;
00689 casb_node_1d <= casb_node;
00690 web_node_1d <= web_node;
00691 end
00692 end
00693 always @(posedge clkx) begin
00694 if (reset) begin
00695 rasb_node_2d <= 1'b1;
00696 casb_node_2d <= 1'b1;
00697 web_node_2d <= 1'b1;
00698 end else begin
00699 rasb_node_2d <= rasb_node_1d;
00700 casb_node_2d <= casb_node_1d;
00701 web_node_2d <= web_node_1d;
00702 end
00703 end
00704 always @(posedge clkx) begin
00705 if (reset) begin
00706 rasb_node_3d <= 1'b1;
00707 casb_node_3d <= 1'b1;
00708 web_node_3d <= 1'b1;
00709 end else begin
00710 rasb_node_3d <= rasb_node_2d;
00711 casb_node_3d <= casb_node_2d;
00712 web_node_3d <= web_node_2d;
00713 end
00714 end
00715
00716 assign ddr2_rasb = rasb_node_3d;
00717 assign ddr2_casb = casb_node_3d;
00718 assign ddr2_web = web_node_3d;
00719
00720 always @ * begin
00721 case (c_state)
00722 READ : begin
00723 ddr2_addr_node <= {1'b0, 1'b0 , 1'b0, column_addr};
00724 bank_addr_node <= bank_addr;
00725 end
00726 WRIT : begin // オートプリチャージ無し
00727 ddr2_addr_node <= {1'b0, 1'b0 , 1'b0, column_addr};
00728 bank_addr_node <= bank_addr;
00729 end
00730 ACT : begin
00731 ddr2_addr_node <= row_addr;
00732 bank_addr_node <= bank_addr;
00733 end
00734 PALL : begin
00735 ddr2_addr_node <= {2'bXX, 1'b1 ,10'bX};
00736 bank_addr_node <= 2'bX;
00737 end
00738 MRS : begin
00739 if (c_init==mrs_dllrst_init)
00740 ddr2_addr_node <= 13'b0_0101_0011_0010; // PD Mode = Fast Exit, Write Recovery = 3 (オート・プリチャージコマンドは使用しない), DLL Rest = Yes, TM = Normal, CAS# Latency = 3, Burst Type = Sequential, Burst Length = 4
00741 else // それ以外
00742 ddr2_addr_node <= 13'b0_0100_0011_0010;
00743 bank_addr_node <= 2'b00;
00744 end
00745 EMRS : begin
00746 if (c_init==emr2s_init) begin // EMR(2)
00747 ddr2_addr_node <= 13'b0_0000_0000_0000;
00748 bank_addr_node <= 2'b10;
00749 end else if (c_init==emr3s_init) begin // EMR(3)
00750 ddr2_addr_node <= 13'b0_0000_0000_0000;
00751 bank_addr_node <= 2'b11;
00752 end else if (c_init==emrs_dllena_init || c_init==emrs_ocd_exit_init) begin // EMR, Output Disable, RDQS Disable, DQS# Enable, OCD = "000", RTT = 75?, Posted CAS = 0 (Posted CASは使用しない), Output Drive Strength = Full Strength, DLL Enable
00753 ddr2_addr_node <= 13'b0_0000_0000_0100;
00754 bank_addr_node <= 2'b01;
00755 end else begin // EMR Output Enable, RDQS Disable, DQS# Enable, OCD = "111", RTT = 75&;, Posted CAS = 0 (Posted CASは使用しない), Output Drive Strength = Full Strength, DLL Enable
00756 ddr2_addr_node <= 13'b0_0011_1000_0100;
00757 bank_addr_node <= 2'b01;
00758 end
00759 end
00760 default : begin // REF, NOP
00761 ddr2_addr_node <= {13{1'bx}};
00762 bank_addr_node <= 2'bxx;
00763 end
00764 endcase
00765 end
00766 always @(posedge clk) begin
00767 if (reset) begin
00768 ddr2_addr_node_1d <= 0;
00769 bank_addr_node_1d <= 0;
00770 end else begin
00771 ddr2_addr_node_1d <= ddr2_addr_node;
00772 bank_addr_node_1d <= bank_addr_node;
00773 end
00774 end
00775 always @(posedge clkx) begin
00776 if (reset) begin
00777 ddr2_addr_node_2d <= 0;
00778 bank_addr_node_2d <= 0;
00779 end else begin
00780 ddr2_addr_node_2d <= ddr2_addr_node_1d;
00781 bank_addr_node_2d <= bank_addr_node_1d;
00782 end
00783 end
00784 always @(posedge clkx) begin
00785 if (reset) begin
00786 ddr2_addr_node_3d <= 0;
00787 bank_addr_node_3d <= 0;
00788 end else begin
00789 ddr2_addr_node_3d <= ddr2_addr_node_2d;
00790 bank_addr_node_3d <= bank_addr_node_2d;
00791 end
00792 end
00793 assign ddr2_address = ddr2_addr_node_3d;
00794 assign ddr2_ba = bank_addr_node_3d;
00795
00796 assign write_timing = (c_state==WRIT) ? 1'b1 : 1'b0;
00797 // assign read_timing = read_timing_node[CAS_LATENCY-1];
00798 assign read_timing = read_timing_node[CAS_LATENCY];
00799 assign read_timing_1b = read_timing_node[CAS_LATENCY-1];
00800 assign read_timing_2b = read_timing_node[CAS_LATENCY-2];
00801
00802 always @(posedge clk) begin // read commandの発行タイミング、casb_node_3dなどを使うとIOBに入らなくなるのでその前のnode_1dから生成する。
00803 if (reset)
00804 read_cmd_issue <= 1'b0;
00805 else if (casb_node_2d==1'b0 && rasb_node_2d==1'b1 && web_node_2d==1'b1)
00806 read_cmd_issue <= 1'b1;
00807 else
00808 read_cmd_issue <= 1'b0;
00809 end
00810 always @(posedge clk) begin // read_cmd_issueの1クロック遅延した信号
00811 if (reset)
00812 read_cmd_issue_1d <= 1'b0;
00813 else
00814 read_cmd_issue_1d <= read_cmd_issue;
00815 end
00816
00817 always @(posedge clk) begin : Read_Timig_Gen_Loop
00818 integer i;
00819
00820 if (reset) begin
00821 read_timing_node <= 0;
00822 end else begin
00823 for (i=0; i<=CAS_LATENCY; i=i+1) begin
00824 if (i==0) begin
00825 if (read_cmd_issue || read_cmd_issue_1d)
00826 read_timing_node[0] <= 1'b1;
00827 else
00828 read_timing_node[0] <= 1'b0;
00829 end else
00830 read_timing_node[i] <= read_timing_node[i-1];
00831 end
00832 end
00833 end
00834
00835 always @(posedge clk) begin
00836 if (reset) begin
00837 b_state <= NOP;
00838 b2_state <= NOP;
00839 end else begin
00840 b_state <= c_state;
00841 b2_state <= b_state;
00842 end
00843 end
00844 assign burst_read = (c_init==init_end && c_state==READ && b_state==READ) ? 1'b1 : 1'b0;
00845
00846 always @(posedge clk) begin
00847 if (reset)
00848 dqs_reset <= 1'b0;
00849 else begin
00850 if (c_state==WRIT && b2_state!=WRIT)
00851 dqs_reset <= 1'b1;
00852 else
00853 dqs_reset <= 1'b0;
00854 end
00855 end
00856
00857 always @(posedge clk) begin
00858 if (reset)
00859 cs_dets <= idle_dets;
00860 else
00861 cs_dets <= ns_dets;
00862 end
00863 always @ * begin
00864 case (cs_dets)
00865 idle_dets : begin
00866 dqs_enable <= 1'b0;
00867 if (c_state==WRIT)
00868 ns_dets <= write_dets;
00869 else
00870 ns_dets <= idle_dets;
00871 end
00872 write_dets : begin
00873 dqs_enable <= 1'b1;
00874 ns_dets <= write_wait;
00875 end
00876 write_wait : begin
00877 dqs_enable <= 1'b1;
00878 if (c_state==WRIT)
00879 ns_dets <= write_dets;
00880 else
00881 ns_dets <= idle_dets;
00882 end
00883 endcase
00884 end
00885
00886 always @(posedge clk) begin
00887 if (reset) begin
00888 initialize_end <= 1'b0;
00889 end else begin
00890 if (c_init==init_end)
00891 initialize_end <= 1'b1;
00892 end
00893 end
00894
00895
00896 `ifdef DDR2_ODT_ENABLE
00897 always @(posedge clkx) begin
00898 if (reset)
00899 cs_odt <= IDLE_ODT;
00900 else
00901 cs_odt <= ns_odt;
00902 end
00903
00904 always @ * begin
00905 case (cs_odt)
00906 IDLE_ODT : begin
00907 odt_node <= 1'b0;
00908 if (write_timing)
00909 ns_odt <= WRITE_ACTIVE;
00910 else
00911 ns_odt <= IDLE_ODT;
00912 end
00913 WRITE_ACTIVE : begin
00914 odt_node <= 1'b1;
00915 ns_odt <= WRITE_TEST;
00916 end
00917 WRITE_TEST : begin
00918 odt_node <= 1'b1;
00919 if (write_timing)
00920 ns_odt <= WRITE_ACTIVE;
00921 else
00922 ns_odt <= WRITE_HOLDOFF1;
00923 end
00924 WRITE_HOLDOFF1: begin
00925 odt_node <= 1'b1;
00926 ns_odt <= IDLE_ODT;
00927 end
00928 endcase
00929 end
00930
00931 always @(posedge clkx) begin
00932 if (reset)
00933 odt_node_1d <= 1'b0;
00934 else
00935 odt_node_1d <= odt_node;
00936 end
00937 assign ddr2_odt = odt_node_1d;
00938 `else
00939 assign ddr2_odt = 1'b0;
00940 `endif
00941
00942
00943 reg [20*8:1] MAIN_STATE, INIT_STATE, STATE_DETS, ODT_STATE;
00944
00945 always @(c_state) begin
00946 case (c_state)
00947 NOP: MAIN_STATE <= "NOP";
00948 ACT: MAIN_STATE <= "ACT";
00949 READ: MAIN_STATE <= "READ";
00950 WRIT: MAIN_STATE <= "WRIT";
00951 PALL: MAIN_STATE <= "PALL";
00952 MRS: MAIN_STATE <= "MRS";
00953 EMRS: MAIN_STATE <= "EMRS";
00954 default: MAIN_STATE <= "REF";
00955 endcase
00956 end
00957
00958 always @(c_init) begin
00959 case (c_init)
00960 idle_init: INIT_STATE <= "IDLE_INIT";
00961 pall1_init: INIT_STATE <= "PALL1_INIT";
00962 emr2s_init: INIT_STATE <= "EMR2S_INIT";
00963 emr3s_init: INIT_STATE <= "EMR3S_INIT";
00964 emrs_dllena_init: INIT_STATE <= "EMRS_DLLENA_INIT";
00965 mrs_dllrst_init: INIT_STATE <= "MRS_DLLRST_INIT";
00966 pall2_init: INIT_STATE <= "PALL2_INIT";
00967 ref1_init: INIT_STATE <= "REF1_INIT";
00968 ref2_init: INIT_STATE <= "REF2_INIT";
00969 mrs_init: INIT_STATE <= "MRS_INIT";
00970 emrs_ocd_def_init: INIT_STATE <= "EMRS_OCD_DEF_INIT";
00971 emrs_ocd_exit_init: INIT_STATE <= "EMRS_OCD_EXIT_INIT";
00972 wait_init_end: INIT_STATE <= "WAIT_INIT_END";
00973 default: INIT_STATE <= "INIT_END";
00974 endcase
00975 end
00976
00977 always @(cs_dets) begin
00978 case(cs_dets)
00979 idle_dets: STATE_DETS <= "IDLE_DETS";
00980 write_dets: STATE_DETS <= "WRITE_DETS";
00981 default: STATE_DETS <= "WRITE_WAIT";
00982 endcase
00983 end
00984
00985 always @(cs_odt) begin
00986 case (cs_odt)
00987 IDLE_ODT: ODT_STATE <= "IDLE_ODT";
00988 WRITE_ACTIVE: ODT_STATE <= "WRITE_ACTIVE";
00989 WRITE_TEST : ODT_STATE <= "WRITE_TEST";
00990 default: ODT_STATE <= "WRITE_HOLDOFF1";
00991 endcase
00992 end
00993
00994 endmodule
00995