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00010 `timescale 1s/1s
00011
00012 module refreqsm(CLK,ref_state,ref_then_by_now,RESET,ref_req);
00013
00014 input CLK;
00015 input ref_state,ref_then_by_now,RESET;
00016 output ref_req;
00017 reg ref_req,next_ref_req;
00018 reg hold_off,next_hold_off,idle,next_idle,ref_req_asert,next_ref_req_asert;
00019
00020 always @(posedge CLK)
00021 begin
00022 if ( RESET ) hold_off = 0;
00023 else hold_off = next_hold_off;
00024 end
00025
00026 always @(posedge CLK)
00027 begin
00028 if ( RESET ) idle = 1;
00029 else idle = next_idle;
00030 end
00031
00032 always @(posedge CLK)
00033 begin
00034 if ( RESET ) ref_req_asert = 0;
00035 else ref_req_asert = next_ref_req_asert;
00036 end
00037
00038 always @(posedge CLK)
00039 begin
00040 if ( RESET ) ref_req = 0;
00041 else ref_req = next_ref_req;
00042 end
00043
00044 always @ (hold_off or idle or ref_req_asert or ref_state or ref_then_by_now
00045 or RESET)
00046 begin
00047
00048 if ( ref_then_by_now & ~RESET & hold_off | ~RESET & ref_state &
00049 ref_req_asert ) next_hold_off=1;
00050 else next_hold_off=0;
00051
00052 if ( ~ref_then_by_now & hold_off | ~ref_then_by_now & idle | RESET )
00053 next_idle=1;
00054 else next_idle=0;
00055
00056 if ( ~RESET & ref_then_by_now & idle | ~ref_state & ~RESET & ref_req_asert
00057 ) next_ref_req_asert=1;
00058 else next_ref_req_asert=0;
00059
00060
00061 if ( ~RESET & ref_then_by_now & idle | ~ref_state & ~RESET & ref_req_asert
00062 ) next_ref_req=1;
00063 else next_ref_req=0;
00064 end
00065 endmodule