00001
00002 `default_nettype none
00003 `timescale 1ps / 1ps
00004
00005 module DDR2_burst_test_tb;
00006
00007 `include "ddr2_parameters.vh"
00008 `include "./ddr2_cont_parameters.vh"
00009
00010 wire [DQ_BITS-1:0] dq;
00011 wire [DQS_BITS-1:0] dqs;
00012 reg reset;
00013 wire [DQS_BITS-1:0] ddr2_dqs_fpga, ddr2_dqs_sdram;
00014 wire [DQS_BITS-1:0] ddr2_dqs_n_fpga, ddr2_dqs_n_sdram;
00015 wire [DQ_BITS-1:0] ddr2_dq_fpga, ddr2_dq_sdram;
00016 reg [DQS_BITS-1:0] ddr2_dqs_fpgan, ddr2_dqs_sdramn;
00017 reg [DQS_BITS-1:0] ddr2_dqs_n_fpgan, ddr2_dqs_n_sdramn;
00018 reg [DQ_BITS-1:0] ddr2_dq_fpgan, ddr2_dq_sdramn;
00019 wire ddr2_clk, ddr2_clkb;
00020 wire ddr2_cke, ddr2_csb, ddr2_rasb, ddr2_casb, ddr2_web;
00021 wire [DM_BITS-1:0] ddr2_dm;
00022 wire [1:0] ddr2_ba;
00023 wire [ADDR_BITS-1:0] ddr2_address;
00024 reg enable_o;
00025 reg clk;
00026 wire [2:0] cmd;
00027 reg sdram_clk;
00028 reg sdram_clkb;
00029 reg [12:0] sdram_address;
00030 reg [1:0] sdram_ba;
00031 reg sdram_cke;
00032 reg sdram_csb, sdram_rasb, sdram_casb, sdram_web;
00033 reg [1:0] sdram_dmn;
00034 wire [1:0] sdram_dm;
00035 wire [3:0] LED;
00036 reg sd_loop_in;
00037 wire sd_loop_out;
00038
00039 parameter DELAY_TIME = 1500;
00040 parameter CLK_PERIOD = 20000;
00041
00042 assign cmd = {ddr2_rasb, ddr2_casb, ddr2_web};
00043
00044 always @(posedge ddr2_clk, posedge reset)
00045 if (reset)
00046 enable_o <= 1'b0;
00047 else
00048 if (cmd==3'b100)
00049 enable_o <= 1'b0;
00050 else if (cmd==3'b101)
00051 enable_o <= 1'b1;
00052
00053 always @ *
00054 if (enable_o == 1'b1)
00055 ddr2_dqs_fpgan <= #DELAY_TIME ddr2_dqs_sdram;
00056 else
00057 ddr2_dqs_fpgan <= #DELAY_TIME {DQS_BITS{1'bz}};
00058
00059 always @ *
00060 if (enable_o == 1'b1)
00061 ddr2_dqs_n_fpgan <= #DELAY_TIME ddr2_dqs_n_sdram;
00062 else
00063 ddr2_dqs_n_fpgan <= #DELAY_TIME {DQS_BITS{1'bz}};
00064
00065 always @ *
00066 if (enable_o == 1'b1)
00067 ddr2_dq_fpgan <= #DELAY_TIME ddr2_dq_sdram;
00068 else
00069 ddr2_dq_fpgan <= #DELAY_TIME {DQ_BITS{1'bz}};
00070
00071 always @ *
00072 if (enable_o == 1'b0)
00073 ddr2_dqs_sdramn <= #DELAY_TIME ddr2_dqs_fpga;
00074 else
00075 ddr2_dqs_sdramn <= #DELAY_TIME {DQS_BITS{1'bz}};
00076
00077 always @ *
00078 if (enable_o == 1'b0)
00079 ddr2_dqs_n_sdramn <= #DELAY_TIME ddr2_dqs_n_fpga;
00080 else
00081 ddr2_dqs_n_sdramn <= #DELAY_TIME {DQS_BITS{1'bz}};
00082
00083 always @ *
00084 if (enable_o == 1'b0)
00085 ddr2_dq_sdramn <= #DELAY_TIME ddr2_dq_fpga;
00086 else
00087 ddr2_dq_sdramn <= #DELAY_TIME {DQ_BITS{1'bz}};
00088
00089 assign ddr2_dqs_fpga = ddr2_dqs_fpgan;
00090 assign ddr2_dqs_n_fpga = ddr2_dqs_n_fpgan;
00091 assign ddr2_dq_fpga = ddr2_dq_fpgan;
00092 assign ddr2_dqs_sdram = ddr2_dqs_sdramn;
00093 assign ddr2_dqs_n_sdram = ddr2_dqs_n_sdramn;
00094 assign ddr2_dq_sdram = ddr2_dq_sdramn;
00095
00096 always @ * begin
00097 sdram_clk <= #DELAY_TIME ddr2_clk;
00098 sdram_clkb <= #DELAY_TIME ddr2_clkb;
00099 sdram_address <= #DELAY_TIME ddr2_address;
00100 sdram_ba <= #DELAY_TIME ddr2_ba;
00101 sdram_cke <= #DELAY_TIME ddr2_cke;
00102 sdram_csb <= #DELAY_TIME ddr2_csb;
00103 sdram_rasb <= #DELAY_TIME ddr2_rasb;
00104 sdram_casb <= #DELAY_TIME ddr2_casb;
00105 sdram_web <= #DELAY_TIME ddr2_web;
00106 sdram_dmn <= #DELAY_TIME ddr2_dm;
00107 end
00108
00109 always @* begin // from sd_loop_in to sd_loop_out delay
00110 sd_loop_in <= #(DELAY_TIME*2) sd_loop_out;
00111 end
00112
00113 DDR2_burst_test DDR2_burst_test_inst(
00114 .SYS_CLK(clk),
00115 .SYS_RST(reset),
00116 .LED(LED),
00117
00118 .ddr2_clk(ddr2_clk),
00119 .ddr2_clkb(ddr2_clkb),
00120 .ddr2_cke(ddr2_cke),
00121 .ddr2_dqs(ddr2_dqs_fpga),
00122 .ddr2_dqs_n(ddr2_dqs_n_fpga),
00123 .ddr2_dq(ddr2_dq_fpga),
00124 .ddr2_csb(ddr2_csb),
00125 .ddr2_rasb(ddr2_rasb),
00126 .ddr2_casb(ddr2_casb),
00127 .ddr2_web(ddr2_web),
00128 .ddr2_dm(ddr2_dm),
00129 .ddr2_ba(ddr2_ba),
00130 .ddr2_address(ddr2_address),
00131 .sd_loop_in(sd_loop_in),
00132 .sd_loop_out(sd_loop_out)
00133 );
00134
00135 assign sdram_dm = sdram_dmn;
00136
00137 ddr2 MT47H16M16_inst(
00138 .dq(ddr2_dq_sdram),
00139 .dqs(ddr2_dqs_sdram),
00140 .dqs_n(ddr2_dqs_n_sdram),
00141 .rdqs_n(),
00142 .addr(sdram_address),
00143 .ba(sdram_ba),
00144 .ck(sdram_clk),
00145 .ck_n(sdram_clkb),
00146 .cke(sdram_cke),
00147 .cs_n(sdram_csb),
00148 .ras_n(sdram_rasb),
00149 .cas_n(sdram_casb),
00150 .we_n(sdram_web),
00151 .dm_rdqs(sdram_dm)
00152 );
00153
00154 initial begin
00155 reset = 1'b0;
00156 #1000 reset = 1'b1;
00157 #200000 reset = 1'b0;
00158 end
00159
00160 always begin
00161 #(CLK_PERIOD/2) clk = 1'b1 ;
00162 #(CLK_PERIOD/2) clk = 1'b0 ;
00163 end
00164
00165 initial begin
00166 #50000000 $stop;
00167 end
00168 endmodule
00169
00170