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00007 `default_nettype none
00008 `timescale 1ns / 1ps
00009
00010 module DDR2_burst_test(SYS_CLK, SYS_RST, LED, ddr2_clk, ddr2_clkb, ddr2_cke, ddr2_dqs, ddr2_dqs_n, ddr2_dq, ddr2_csb, ddr2_rasb, ddr2_casb, ddr2_web, ddr2_dm, ddr2_ba, ddr2_address, ddr2_odt, sd_loop_in, sd_loop_out);
00011
00012 `include "./ddr2_cont_parameters.vh"
00013
00014 input SYS_CLK;
00015 input SYS_RST;
00016 output [3:0] LED;
00017
00018 output [QUANTITY_OF_CLK_OUTPUT-1 : 0] ddr2_clk;
00019 output [QUANTITY_OF_CLK_OUTPUT-1 : 0] ddr2_clkb;
00020 output ddr2_cke;
00021 inout [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dqs;
00022 inout [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dqs_n;
00023 inout [DDR2_DATA_WIDTH-1 : 0] ddr2_dq;
00024 output ddr2_csb;
00025 output ddr2_rasb;
00026 output ddr2_casb;
00027 output ddr2_web;
00028 output [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dm;
00029 output [1:0] ddr2_ba;
00030 output [DDR2_ADDRESS_WIDTH-1 : 0] ddr2_address;
00031 output ddr2_odt;
00032 input sd_loop_in;
00033 output sd_loop_out;
00034
00035 wire SYS_CLK;
00036 wire SYS_RST;
00037 wire [3:0] LED;
00038
00039 wire [QUANTITY_OF_CLK_OUTPUT-1 : 0] ddr2_clk;
00040 wire [QUANTITY_OF_CLK_OUTPUT-1 : 0] ddr2_clkb;
00041 wire ddr2_cke;
00042 wire [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dqs;
00043 wire [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dqs_n;
00044 wire [DDR2_DATA_WIDTH-1 : 0] ddr2_dq;
00045 wire ddr2_csb;
00046 wire ddr2_rasb;
00047 wire ddr2_casb;
00048 wire ddr2_web;
00049 wire [DDR2_DQS_DM_WIDTH-1 : 0] ddr2_dm;
00050 wire [1:0] ddr2_ba;
00051 wire [DDR2_ADDRESS_WIDTH-1 : 0] ddr2_address;
00052 wire ddr2_odt;
00053 wire sd_loop_in;
00054 wire sd_loop_out;
00055
00056 wire logic0, logic1;
00057 reg [INTERFACE_DATA_WIDTH-1 : 0] input_data;
00058 wire [INTERFACE_MASK_WIDTH-1 : 0] input_mask;
00059 wire read_write;
00060 reg [USER_INPUT_ADDRESS_WIDTH-1 : 0] input_address;
00061 wire addr_fifo_wren;
00062 wire wrdata_fifo_wren;
00063 wire addr_fifo_full;
00064 wire wrdata_fifo_full;
00065 wire rddata_valid;
00066 wire initialize_end;
00067 wire [15:0] DDR_write_data, DDR_read_data;
00068 wire sw_ena;
00069 wire read_ddr_cont;
00070 wire [INTERFACE_DATA_WIDTH-1 : 0] output_data;
00071 wire read_write_node, addr_fifo_wren_node, wrdata_fifo_wren_node;
00072 wire clk;
00073 reg [6:0] cs, ns;
00074 reg [7:0] burst_length, write_counter, read_counter;
00075 reg read_error;
00076 reg [USER_INPUT_ADDRESS_WIDTH-1 : 0] temp_in_addr;
00077 reg [INTERFACE_DATA_WIDTH-1 : 0] expected_read_data;
00078 wire dcm_locked_out;
00079 wire reset;
00080 reg [3:0] nLED;
00081 wire clk_sdram, dcm_locked_200;
00082
00083 parameter IDLE = 7'b0000001,
00084 ADDRESS_LOAD = 7'b0000010,
00085 DATA_WRITE1 = 7'b0000100,
00086 DATA_WRITE2 = 7'b0001000,
00087 DATA_READ1 = 7'b0010000,
00088 DATA_READ2 = 7'b0100000,
00089 ERROR_DET = 7'b1000000;
00090
00091 parameter LIMIT_OF_BURST_LENGTH = 8'd16;
00092
00093 assign logic0 = 1'b0;
00094 assign logic1 = 1'b1;
00095 assign reset = SYS_RST | ~dcm_locked_out;
00096 assign LED = ~nLED;
00097
00098 dcm_DDR2_clk dcm_DDR2_clk_inst(
00099 .sysclk(SYS_CLK),
00100 .reset(reset),
00101 .clk_sdram(clk_sdram),
00102 .dcm_locked_out(dcm_locked_200)
00103 );
00104
00105 ddr2_sdram_cont ddr2_sdram_cont_inst (
00106 .sysclk(clk_sdram),
00107 .clk_out(clk),
00108 .reset(SYS_RST),
00109 .input_data(input_data),
00110 .input_mask(input_mask),
00111 .read_write(read_write),
00112 .output_data(output_data),
00113 .input_address(input_address),
00114 .addr_fifo_wren(addr_fifo_wren),
00115 .wrdata_fifo_wren(wrdata_fifo_wren),
00116 .addr_fifo_full(addr_fifo_full),
00117 .wrdata_fifo_full(wrdata_fifo_full),
00118 .rddata_valid(rddata_valid),
00119 .initialize_end(initialize_end),
00120 .dcm_locked_in(dcm_locked_200),
00121 .dcm_locked_out(dcm_locked_out),
00122 .ddr2_clk(ddr2_clk),
00123 .ddr2_clkb(ddr2_clkb),
00124 .ddr2_cke(ddr2_cke),
00125 .ddr2_dqs(ddr2_dqs),
00126 .ddr2_dqs_n(ddr2_dqs_n),
00127 .ddr2_dq(ddr2_dq),
00128 .ddr2_csb(ddr2_csb),
00129 .ddr2_rasb(ddr2_rasb),
00130 .ddr2_casb(ddr2_casb),
00131 .ddr2_web(ddr2_web),
00132 .ddr2_dm(ddr2_dm),
00133 .ddr2_ba(ddr2_ba),
00134 .ddr2_address(ddr2_address),
00135 .ddr2_odt(ddr2_odt),
00136 .sd_loop_in(sd_loop_in),
00137 .sd_loop_out(sd_loop_out)
00138 );
00139
00140 assign input_mask = 0;
00141
00142 always @(posedge clk, posedge reset) begin
00143 if (reset)
00144 input_data <= 0;
00145 else
00146 if ((cs==DATA_WRITE1 || cs==DATA_WRITE2) && !addr_fifo_full && !wrdata_fifo_full)
00147 input_data <= input_data + 1;
00148 end
00149
00150
00151 always @(posedge clk, posedge reset) begin
00152 if (reset)
00153 cs <= IDLE;
00154 else
00155 cs <= ns;
00156 end
00157 always @* begin
00158 nLED[3:2] <= 2'b11;
00159 case (cs)
00160 IDLE : begin
00161 nLED[0] <= 1'b0; nLED[1] <= 1'b1;
00162 if (read_error)
00163 ns <= ERROR_DET;
00164 else if (initialize_end)
00165 ns <= ADDRESS_LOAD;
00166 else
00167 ns <= IDLE;
00168 end
00169 ADDRESS_LOAD : begin
00170 nLED[0] <= 1'b0; nLED[1] <= 1'b1;
00171 ns <= DATA_WRITE1;
00172 end
00173 DATA_WRITE1 : begin
00174 nLED[0] <= 1'b0; nLED[1] <= 1'b1;
00175 if (read_error)
00176 ns <= ERROR_DET;
00177 else if (!addr_fifo_full && !wrdata_fifo_full)
00178 ns <= DATA_WRITE2;
00179 else
00180 ns <= DATA_WRITE1;
00181 end
00182 DATA_WRITE2 : begin
00183 nLED[0] <= 1'b0; nLED[1] <= 1'b1;
00184 if (read_error)
00185 ns <= ERROR_DET;
00186 else if (write_counter==1) begin
00187 if (!addr_fifo_full && !wrdata_fifo_full)
00188 ns <= DATA_READ1;
00189 else
00190 ns <= DATA_WRITE2;
00191 end else begin
00192 if (!addr_fifo_full && !wrdata_fifo_full)
00193 ns <= DATA_WRITE1;
00194 else
00195 ns <= DATA_WRITE2;
00196 end
00197 end
00198 DATA_READ1 : begin
00199 nLED[0] <= 1'b0; nLED[1] <= 1'b1;
00200 if (read_error)
00201 ns <= ERROR_DET;
00202 else if (!addr_fifo_full)
00203 ns <= DATA_READ2;
00204 else
00205 ns <= DATA_READ1;
00206 end
00207 DATA_READ2 : begin
00208 nLED[0] <= 1'b0; nLED[1] <= 1'b1;
00209 if (read_error)
00210 ns <= ERROR_DET;
00211 else if (read_counter==1) begin
00212 if (!addr_fifo_full)
00213 ns <= ADDRESS_LOAD;
00214 else
00215 ns <= DATA_READ2;
00216 end else
00217 ns <= DATA_READ1;
00218 end
00219 ERROR_DET : begin
00220 nLED[0] <= 1'b1; nLED[1] <= 1'b0;
00221 ns <= ERROR_DET;
00222
00223 $display("リードエラーを検出");
00224 #10 $stop;
00225
00226 end
00227 endcase
00228 end
00229
00230
00231
00232
00233 function [22:0] lfsr23 (input [22:0] data);
00234 reg lsb;
00235
00236
00237
00238 begin
00239 lsb=data[22] ^ data[4];
00240 lfsr23={data[21:0],lsb};
00241 end
00242 endfunction
00243
00244 function [7:0] lfsr8 (input [7:0] data);
00245 reg lsb;
00246
00247
00248 begin
00249 lsb=data[7] ^ data[4]^data[3] ^data[2]^data[0];
00250 lfsr8={data[6:0],lsb};
00251 end
00252 endfunction
00253
00254
00255
00256 function [24:0] get_next_random_address ( input [24:0] old_address);
00257
00258 get_next_random_address=lfsr23(old_address >>2) <<2;
00259 endfunction
00260
00261
00262 always @(posedge clk, posedge reset) begin
00263 if (reset) begin
00264 input_address <= 4;
00265 temp_in_addr <= 4;
00266 end else begin
00267 if (cs == ADDRESS_LOAD) begin
00268 input_address <= get_next_random_address(temp_in_addr);
00269 temp_in_addr <= get_next_random_address(temp_in_addr);
00270 end else if (cs==DATA_WRITE1 || cs==DATA_WRITE2) begin
00271 if (write_counter==8'h01 && !addr_fifo_full && !wrdata_fifo_full)
00272 input_address <= temp_in_addr;
00273 else if (!addr_fifo_full && !wrdata_fifo_full)
00274 input_address <= input_address + 2;
00275 end else if (cs==DATA_READ1 || cs==DATA_READ2) begin
00276 if (read_counter!=8'h01 && !addr_fifo_full)
00277 input_address <= input_address + 2;
00278 end
00279 end
00280 end
00281
00282
00283 always @(posedge clk, posedge reset) begin
00284 if (reset) begin
00285 burst_length <= 1;
00286 write_counter <= 1;
00287 read_counter <= 1;
00288 end else begin
00289 if (cs == ADDRESS_LOAD) begin
00290 if (lfsr8(burst_length) > LIMIT_OF_BURST_LENGTH) begin
00291 burst_length <= 1;
00292 write_counter <= 1;
00293 read_counter <= 1;
00294 end else begin
00295 burst_length <= lfsr8(burst_length);
00296 write_counter <= lfsr8(burst_length);
00297 read_counter <= lfsr8(burst_length);
00298 end
00299 end else if (cs==DATA_WRITE2 && !addr_fifo_full && !wrdata_fifo_full)
00300 write_counter <= write_counter - 1;
00301 else if (cs==DATA_READ2 && !addr_fifo_full)
00302 read_counter <= read_counter - 1;
00303 end
00304 end
00305
00306
00307 always @(posedge clk, posedge reset) begin
00308 if (reset)
00309 expected_read_data <= 0;
00310 else
00311 if (rddata_valid)
00312 expected_read_data <= expected_read_data + 1;
00313 end
00314
00315
00316 always @(posedge clk, posedge reset) begin
00317 if (reset)
00318 read_error <= 1'b0;
00319 else begin
00320
00321
00322 if (rddata_valid && (output_data!=expected_read_data))
00323 read_error <= 1'b1;
00324 else
00325 read_error <= 1'b0;
00326 end
00327 end
00328 assign read_write_node = (cs==DATA_WRITE1 || cs==DATA_WRITE2) ? 1'b0 : 1'b1;
00329 assign addr_fifo_wren_node = ((cs==DATA_WRITE1 && !addr_fifo_full && !wrdata_fifo_full) || (cs==DATA_READ1 && !addr_fifo_full)) ? 1'b1 : 1'b0;
00330 assign wrdata_fifo_wren_node = ((cs==DATA_WRITE1 || cs==DATA_WRITE2) && !addr_fifo_full && !wrdata_fifo_full) ? 1'b1 : 1'b0;
00331
00332 assign
00333
00334 #1
00335
00336 read_write = read_write_node;
00337 assign
00338
00339 #1
00340
00341 addr_fifo_wren = addr_fifo_wren_node;
00342 assign
00343
00344 #1
00345
00346 wrdata_fifo_wren = wrdata_fifo_wren_node;
00347
00348
00349 reg [20*8:1] STATE;
00350
00351 always @(cs) begin
00352 case (cs)
00353 IDLE: STATE <= "IDLE";
00354 ADDRESS_LOAD: STATE <= "ADDRESS_LOAD";
00355 DATA_WRITE1: STATE <= "DATA_WRITE1";
00356 DATA_WRITE2: STATE <= "DATA_WRITE2";
00357 DATA_READ1: STATE <= "DATA_READ1";
00358 DATA_READ2: STATE <= "DATA_READ2";
00359 default: STATE <= "ERROR_DET";
00360 endcase
00361 end
00362
00363 endmodule
00364