00001
00002
00003
00004 `default_nettype none
00005 `timescale 1ns / 1ps
00006
00007 (* KEEP_HIERARCHY = "TRUE" *)module dcm_DDR2_clk (sysclk, reset, clk_sdram, dcm_locked_out);
00008 `include "./ddr2_cont_parameters.vh"
00009 input wire sysclk;
00010 input wire reset;
00011 output wire clk_sdram;
00012 output wire dcm_locked_out;
00013
00014 wire clk_bufg, clk_node, dcm1_locked;
00015 wire clk_sdram_node, clk_sdram_bufg;
00016
00017 DCM dcm_DDR2_clk_dcm (
00018 .CLKIN(sysclk),
00019 .CLKFB(clk_bufg),
00020 .DSSEN(1'b0),
00021 .PSINCDEC(1'b0),
00022 .PSEN(1'b0),
00023 .PSCLK(1'b0),
00024 .RST(1'b0),
00025 .CLK0(clk_node),
00026 .CLK90(),
00027 .CLK180(),
00028 .CLK270(),
00029 .CLK2X(),
00030 .CLK2X180(),
00031 .CLKDV(),
00032 .CLKFX(clk_sdram_node),
00033 .CLKFX180(),
00034 .LOCKED(dcm1_locked),
00035 .PSDONE(),
00036 .STATUS()
00037 );
00038 defparam dcm_DDR2_clk_dcm.CLKIN_PERIOD = 20.0;
00039 defparam dcm_DDR2_clk_dcm.DLL_FREQUENCY_MODE = "LOW";
00040 defparam dcm_DDR2_clk_dcm.DUTY_CYCLE_CORRECTION = "TRUE";
00041 defparam dcm_DDR2_clk_dcm.CLKDV_DIVIDE = 16.0;
00042 defparam dcm_DDR2_clk_dcm.PHASE_SHIFT = 0;
00043 defparam dcm_DDR2_clk_dcm.CLKOUT_PHASE_SHIFT = "NONE";
00044 defparam dcm_DDR2_clk_dcm.STARTUP_WAIT = "FALSE";
00045 defparam dcm_DDR2_clk_dcm.CLKFX_DIVIDE = 1;
00046 defparam dcm_DDR2_clk_dcm.CLKFX_MULTIPLY = 3;
00047
00048
00049 BUFG CLK_BUFG_INST (
00050 .I(clk_node),
00051 .O(clk_bufg)
00052 );
00053
00054 BUFG CLK200_BUFG_INST (
00055 .I(clk_sdram_node),
00056 .O(clk_sdram_bufg)
00057 );
00058 assign clk_sdram = clk_sdram_bufg;
00059 assign dcm_locked_out = dcm1_locked;
00060 endmodule